Responsibilities:

• Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design.
• Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance.
• Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels.
• Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out.
• Collaborate with design engineers to troubleshoot and resolve simulation issues.
• Provide support to test engineers during post-silicon validation.
• Mentor and guide team members and junior engineers, aiming to enhance verification efficiency.​

Requirements:

• Master in Electrical Engineering or equivalent with 8 years of relevant working experience/ PhD in Electrical Engineering or equivalent with 3 years working experience.
• Extensive understanding of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware-software co-verification methodology.
• Skilled in Verilog, SystemVerilog, Python, Perl, TCL, Shell scripting, C/C++, SystemC, and assembly coding for industry-standard ISAs.
• Familiar with MIPI, AMBA (APB/AHB/AXI) bus protocols, RISC-V/ARM, or DSP cores.
• Experience in verifying designs at RTL and post-P&R gate levels.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Responsibilities:

• Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design.
• Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance.
• Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels.
• Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out.
• Collaborate with design engineers to troubleshoot and resolve simulation issues.
• Provide support to test engineers during post-silicon validation.
• Mentor and guide team members and junior engineers, aiming to enhance verification efficiency.​

Requirements:

• Master in Electrical Engineering or equivalent with 8 years of relevant working experience/ PhD in Electrical Engineering or equivalent with 3 years working experience.
• Extensive understanding of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware-software co-verification methodology.
• Skilled in Verilog, SystemVerilog, Python, Perl, TCL, Shell scripting, C/C++, SystemC, and assembly coding for industry-standard ISAs.
• Familiar with MIPI, AMBA (APB/AHB/AXI) bus protocols, RISC-V/ARM, or DSP cores.
• Experience in verifying designs at RTL and post-P&R gate levels.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Position Overview:

As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space.

Requirements:

1. Experience in UVM verification methodology

2. Disciplined, quality-minded, and highly driven for excellence,

3. Excellent team player and good communication skills

4. MSEE/BSEE in Electrical Engineering or Computer Engineering, with 3 years of relevant experience, but are open to fresh graduates with outstanding results

5. Candidates with relevant experiences would be offered as Senior or Staff, taking on higher responsibilities

6. Experience in video processing and video analytics is a plus

7. Passionate and strong in general programming is a plus

Responsibilities:

• Collaborate with Senior Engineers for design requirements and specifications.
• Assist in Analog, mixed-signal, and digital IC design.
• Participate in RTL coding and verification for digital ICs.
• Support design verification tasks.
• Conduct circuit simulations and analysis using Cadence, Synopsys, and Mentor Graphics tools.
• Assist layout engineers with floor planning.
• Analyze and debug silicon failures, suggesting design improvements.
• Contribute to the development of design methodologies to enhance efficiency.
• Document design work and test plans.
• Collaborate with cross-functional teams to ensure successful tape-out.

Requirements:

• Bachelor’s Degree in Electrical Engineering or equivalents.
• At least 2 years of relevant working experience.
• Understanding the IC development flow in advanced CMOS processes, including design, layout, and tape-out.
• Understanding the fundamental theories of digital or analog circuit design.
• Capability to generate inventive designs and circuit solutions tailored to fulfill customer needs.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Responsibilities:

• Lead RTL design, simulation, and verification for TetraMem ASIC/SoC products, ensuring robustness.
• Integrate and validate IP blocks for seamless system functionality.
• Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs.
• Collaborate with backend team in RTL coding, implementation, and synthesis for successful tapeout.
• Create and maintain reusable IPs for AI/in-memory computing.
• Support Post-Si testing to ensure product functionality and quality.
• Mentor junior engineers to facilitate their professional growth.
• Contribute to design reviews for improved product performance and reliability.
• Stay current on RTL design methodologies for efficiency and quality.
• Collaborate with cross-functional teams for successful product development.

Requirements:

• Minimum Master in Electrical Engineering with 5 years of working experience with emphasis on RTL/SoC/digital design.
• Proficient in Verilog and SystemVerilog.
• Proficient in VCS, Verdi, or similar industry-standard tools.
• Skilled in pre-layout and post-layout simulation.
• Knowledgeable about the design flow and collaboration with backend teams.
• Familiar with AMBA APB and AXI protocols.
• Familiar with RISC/Arm or other core architectures.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Responsibilities:

• Collaborate with Senior Engineers for design requirements and specifications.
• Assist in Analog, mixed-signal, and digital IC design.
• Participate in RTL coding and verification for digital ICs.
• Support design verification tasks.
• Conduct circuit simulations and analysis using Cadence, Synopsys, and Mentor Graphics tools.
• Assist layout engineers with floor planning.
• Analyze and debug silicon failures, suggesting design improvements.
• Contribute to the development of design methodologies to enhance efficiency.
• Document design work and test plans.
• Collaborate with cross-functional teams to ensure successful tape-out.

Requirements:

• Bachelor’s Degree in Electrical Engineering or equivalents.
• At least 2 years of relevant working experience.
• Understanding the IC development flow in advanced CMOS processes, including design, layout, and tape-out.
• Understanding the fundamental theories of digital or analog circuit design.
• Capability to generate inventive designs and circuit solutions tailored to fulfill customer needs.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team, ISP Design leaders in other sites, and Digital System Design Team
• Leading, supervising and mentoring a team of RTL design engineers

Requirements

• Minimum MSEE, or BSEE, or equivalent, plus 7+ years of Digital Design and verification related experience
• 3+ years project management / people management experience / skill
• Experience / knowledge in CMOS Image Sensor and image signal processing (ISP)
• Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
• Ability to lead teams and collaborate effectively with people in different functions
• Strong time management skills to ensure timely completion of deliverables
• Good communication and interpersonal skills
• Result oriented and embrace change behaviours

Responsibilities:

• Collaborate with Senior Engineers for design requirements and specifications.
• Assist in Analog, mixed-signal, and digital IC design.
• Participate in RTL coding and verification for digital ICs.
• Support design verification tasks.
• Conduct circuit simulations and analysis using Cadence, Synopsys, and Mentor Graphics tools.
• Assist layout engineers with floor planning.
• Analyze and debug silicon failures, suggesting design improvements.
• Contribute to the development of design methodologies to enhance efficiency.
• Document design work and test plans.
• Collaborate with cross-functional teams to ensure successful tape-out.

Requirements:

• Bachelor’s Degree in Electrical Engineering or equivalents.
• At least 2 years of relevant working experience.
• Understanding the IC development flow in advanced CMOS processes, including design, layout, and tape-out.
• Understanding the fundamental theories of digital or analog circuit design.
• Capability to generate inventive designs and circuit solutions tailored to fulfill customer needs.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Responsibilities:

• Lead RTL design, simulation, and verification for TetraMem ASIC/SoC products, ensuring robustness.
• Integrate and validate IP blocks for seamless system functionality.
• Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs.
• Collaborate with backend team in RTL coding, implementation, and synthesis for successful tapeout.
• Create and maintain reusable IPs for AI/in-memory computing.
• Support Post-Si testing to ensure product functionality and quality.
• Mentor junior engineers to facilitate their professional growth.
• Contribute to design reviews for improved product performance and reliability.
• Stay current on RTL design methodologies for efficiency and quality.
• Collaborate with cross-functional teams for successful product development.

Requirements:

• Minimum Master in Electrical Engineering with 5 years of working experience with emphasis on RTL/SoC/digital design.
• Proficient in Verilog and SystemVerilog.
• Proficient in VCS, Verdi, or similar industry-standard tools.
• Skilled in pre-layout and post-layout simulation.
• Knowledgeable about the design flow and collaboration with backend teams.
• Familiar with AMBA APB and AXI protocols.
• Familiar with RISC/Arm or other core architectures.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

• A1 Main Con
• LTA/Building projects
• 5 working days

Responsibilities:

• Coordinate design drawings with consultants to comply with requirements of the authorities
• Review and provide solutions to technical problems as well as plan, monitor and report shop drawing production progress
• Prepare technical submissions for materials, construction methods and C&S shop drawings
• Resolve construction issues on drawings and liaise closely with Architectural and M&E teams

Requirement:

• Degree in Civil / Structural Engineering or similar
• 3 years of working experience in the related field
• Experience in LTA projects/building projects

Kindly send your updated resume to"[email protected]"

EA Reg. No: R1880058 | Dylan

Your Job

As a Product Design Engineer specializing in IO connectors, your primary focus will be on supporting the development and manufacturing of new products. This will involve collaborating with manufacturing teams to review and provide feedback on the feasibility and plant capability of new concepts. You will also conduct analysis activities such as Proof of Concept (POC), Finite Element Analysis (FEA), and Tolerance Analysis to ensure product performance and integrity.

Our Team

You will be reporting to Manager, Product Design

What You Will Do

• Support of new Product Development and manufacturing for IO connectors.
• Review new concepts with manufacturing and provide feedback on feasibility and plant capability
• Support analysis activities such as POC, FEA and Tolerance Analysis
• Provide alternative solutions to resolve gaps in achieving target specifications
• Manage activities related to FOT, FSV and DVP&R testing
• Support existing product already in production or launching.
• Provide Engineering support of customer quality issues to ensure product reliability
• Provide Engineering support to plant for cost reductions and yield improvements
• Create Product Modifications and series expansions to increase market share
• Other duties as assigned by Management

Who You Are (Basic Qualifications)

• Bachelor’s degree in engineering
• 3 years mechanical product design experience with electronic products
• Experienced with product development process
• Understanding of Tolerance analysis, DFMEA, FEA
• Attention to details, be creative, good interpersonal skills to work effectively with internal cross functional teams and external customers
• Self-starter with confidence to initiate action independently

What Will Put You Ahead

• Bachelor’s degree in mechanical engineering and similar work experience
• From connector industries
• 5 years with specific high speed data connector design knowledge in the commercial or consumer space
• Knowledge of SMT design and signal integrity
• Strong mechanical aptitude and experience with clean sheet new product development component design
• Advanced tolerance stack understanding and risk mitigation skills
• Familiar with the component manufacturing environment, understanding of industry quality standards and requirements
• Basic knowledge on component design (injection, diecasting, sheet metal stamping)

At Koch companies, we are entrepreneurs. This means we openly challenge the status quo, find new ways to create value and get rewarded for our individual contributions. Any compensation range provided for a role is an estimate determined by available market data. The actual amount may be higher or lower than the range provided considering each candidate’s knowledge, skills, abilities, and geographic location. If you have questions, please speak to your recruiter about the flexibility and detail of our compensation philosophy.

Who We Are

As a Koch company, Molex is a leading supplier of connectors and interconnect components, driving innovation in electronics and supporting industries from automotive to health care and consumer to data communications. The thousands of innovators who work for Molex have made us a global electronics leader. Our experienced people, groundbreaking products and leading-edge technologies help us deliver a wider array of solutions to more markets than ever before.

At Koch, employees are empowered to do what they do best to make life better. Learn how our business philosophy helps employees unleash their potential while creating value for themselves and the company.

Additionally, everyone has individual work and personal needs. We seek to enable the best work environment that helps you and the business work together to produce superior results.

Your Job

As a Product Design Engineer specializing in IO connectors, your primary focus will be on supporting the development and manufacturing of new products. This will involve collaborating with manufacturing teams to review and provide feedback on the feasibility and plant capability of new concepts. You will also conduct analysis activities such as Proof of Concept (POC), Finite Element Analysis (FEA), and Tolerance Analysis to ensure product performance and integrity.

Our Team

You will be reporting to Manager, Product Design

What You Will Do

• Support of new Product Development and manufacturing for IO connectors.
• Review new concepts with manufacturing and provide feedback on feasibility and plant capability
• Support analysis activities such as POC, FEA and Tolerance Analysis
• Provide alternative solutions to resolve gaps in achieving target specifications
• Manage activities related to FOT, FSV and DVP&R testing
• Support existing product already in production or launching.
• Provide Engineering support of customer quality issues to ensure product reliability
• Provide Engineering support to plant for cost reductions and yield improvements
• Create Product Modifications and series expansions to increase market share
• Other duties as assigned by Management

Who You Are (Basic Qualifications)

• Bachelor’s degree in engineering
• 3 years mechanical product design experience with electronic products
• Experienced with product development process
• Understanding of Tolerance analysis, DFMEA, FEA
• Attention to details, be creative, good interpersonal skills to work effectively with internal cross functional teams and external customers
• Self-starter with confidence to initiate action independently

What Will Put You Ahead

• Bachelor’s degree in mechanical engineering and similar work experience
• From connector industries
• 5 years with specific high speed data connector design knowledge in the commercial or consumer space
• Knowledge of SMT design and signal integrity
• Strong mechanical aptitude and experience with clean sheet new product development component design
• Advanced tolerance stack understanding and risk mitigation skills
• Familiar with the component manufacturing environment, understanding of industry quality standards and requirements
• Basic knowledge on component design (injection, diecasting, sheet metal stamping)

At Koch companies, we are entrepreneurs. This means we openly challenge the status quo, find new ways to create value and get rewarded for our individual contributions. Any compensation range provided for a role is an estimate determined by available market data. The actual amount may be higher or lower than the range provided considering each candidate’s knowledge, skills, abilities, and geographic location. If you have questions, please speak to your recruiter about the flexibility and detail of our compensation philosophy.

Who We Are

As a Koch company, Molex is a leading supplier of connectors and interconnect components, driving innovation in electronics and supporting industries from automotive to health care and consumer to data communications. The thousands of innovators who work for Molex have made us a global electronics leader. Our experienced people, groundbreaking products and leading-edge technologies help us deliver a wider array of solutions to more markets than ever before.

At Koch, employees are empowered to do what they do best to make life better. Learn how our business philosophy helps employees unleash their potential while creating value for themselves and the company.

Additionally, everyone has individual work and personal needs. We seek to enable the best work environment that helps you and the business work together to produce superior results.

JOB DESCRIPTION

· Discussion with system engineers on SoC architecture and feedback on optimization.

· Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;

· Discussion with synthesis engineer and back-end engineer on design optimization.

· SoC DFT support;

· SoC verification plan and SoC verification support

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Knowledge of ASIC design flow

· Experience in RTL coding, RTL and gate-level debug

· Understanding of DFT, timing and power requirements

· Familiar with UNIX/ Linux environment and scripting

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills

· Knowledge on mixed-signal design would be an advantage.

JOB DESCRIPTION

· Discussion with system engineers on IP requirement and micro architecture.

· Develop IP (control path intensive or data path intensive) meet functional requirement and protocol standard.

· Support SoC designer on integration, timing constraints and power domain setting.

· Support IP verification for verification plan review, test case debugging.

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Experience in IP development (either control path intensive or data path intensive)

· Knowledge of timing, DFT and power structure.

· Familiar with UNIX/ Linux environment and scripting

· Experience on communication IP and/or video IP development would be advantage.

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills

· Experience on communication IP development would be an advantage

· Experience on video IP development would be an advantage

JOB DESCRIPTION

· Work with system engineers on timing requirements and feedback on optimization.

· Work on SoC timing constraint, synthesis and timing closure.

· Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains

· Conduct formal verification for release comparison.

· Support back-end implementation on timing violation analysis and fix.

· Support scan insertion and optimization.

· Support on power structure and power optimization.

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Familiar with ASIC design flow

· Experience in logic synthesis, static timing analysis, timing closure

· Good understanding of DFT and Power structure.

· Familiar with UNIX/ Linux environment and scripting

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills

Responsibilities:

• Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design.
• Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance.
• Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels.
• Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out.
• Collaborate with design engineers to troubleshoot and resolve simulation issues.
• Provide support to test engineers during post-silicon validation.
• Mentor and guide team members and junior engineers, aiming to enhance verification efficiency.​

Requirements:

• Master in Electrical Engineering or equivalent with 8 years of relevant working experience/ PhD in Electrical Engineering or equivalent with 3 years working experience.
• Extensive understanding of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware-software co-verification methodology.
• Skilled in Verilog, SystemVerilog, Python, Perl, TCL, Shell scripting, C/C++, SystemC, and assembly coding for industry-standard ISAs.
• Familiar with MIPI, AMBA (APB/AHB/AXI) bus protocols, RISC-V/ARM, or DSP cores.
• Experience in verifying designs at RTL and post-P&R gate levels.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Responsibilities:

• Collaborate with Senior Engineers for design requirements and specifications.
• Assist in Analog, mixed-signal, and digital IC design.
• Participate in RTL coding and verification for digital ICs.
• Support design verification tasks.
• Conduct circuit simulations and analysis using Cadence, Synopsys, and Mentor Graphics tools.
• Assist layout engineers with floor planning.
• Analyze and debug silicon failures, suggesting design improvements.
• Contribute to the development of design methodologies to enhance efficiency.
• Document design work and test plans.
• Collaborate with cross-functional teams to ensure successful tape-out.

Requirements:

• Bachelor’s Degree in Electrical Engineering or equivalents.
• At least 2 years of relevant working experience.
• Understanding the IC development flow in advanced CMOS processes, including design, layout, and tape-out.
• Understanding the fundamental theories of digital or analog circuit design.
• Capability to generate inventive designs and circuit solutions tailored to fulfill customer needs.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Job Responsibilities:

1. Design of commercial, residential, industrial buildings in precast.
2. To liaise and coordinate with consultants and main-contractor on project details and resolving technical issues.
3. Accountable for the preparation and completion of precast shop drawings with specific time and meets all clients’ requirements.
4. Accountable for accuracy and updating amendments to precast shop drawings.
5. Attend meetings with consultants and main-contractor as well as site meetings.
6. Manage drafting staff and check drawings to ensure compliance with design concept.
7. Manage, plan and schedule projects, shop drawings for submission and production.
8. To liaise internally with coordinator and production on submission/issuance of shop drawings any technical issue and keep them updated of any revision.
9. Conduct review on details of design to ensure the accuracy of shop drawings produced.

Job Requirements:

1. Bachelor degree in Civil & Structural Engineering from recognised University.
2. 3 years working experience in construction design.
3. Familiar with design analysis software such as Etabs, Prokon etc.
4. Good communication skills.

Job Responsibilities:

1. Design of commercial, residential, industrial buildings in precast.
2. To liaise and coordinate with consultants and main-contractor on project details and resolving technical issues.
3. Accountable for the preparation and completion of precast shop drawings with specific time and meets all clients’ requirements.
4. Accountable for accuracy and updating amendments to precast shop drawings.
5. Attend meetings with consultants and main-contractor as well as site meetings.
6. Manage drafting staff and check drawings to ensure compliance with design concept.
7. Manage, plan and schedule projects, shop drawings for submission and production.
8. To liaise internally with coordinator and production on submission/issuance of shop drawings any technical issue and keep them updated of any revision.
9. Conduct review on details of design to ensure the accuracy of shop drawings produced.

Job Requirements:

1. Bachelor degree in Civil & Structural Engineering from recognised University.
2. 3 years working experience in construction design.
3. Familiar with design analysis software such as Etabs, Prokon etc.
4. Good communication skills.

Responsibilities:

• Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design.
• Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance.
• Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels.
• Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out.
• Collaborate with design engineers to troubleshoot and resolve simulation issues.
• Provide support to test engineers during post-silicon validation.
• Mentor and guide team members and junior engineers, aiming to enhance verification efficiency.​

Requirements:

• Master in Electrical Engineering or equivalent with 8 years of relevant working experience/ PhD in Electrical Engineering or equivalent with 3 years working experience.
• Extensive understanding of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware-software co-verification methodology.
• Skilled in Verilog, SystemVerilog, Python, Perl, TCL, Shell scripting, C/C++, SystemC, and assembly coding for industry-standard ISAs.
• Familiar with MIPI, AMBA (APB/AHB/AXI) bus protocols, RISC-V/ARM, or DSP cores.
• Experience in verifying designs at RTL and post-P&R gate levels.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Responsibilities:

• Collaborate with Senior Engineers for design requirements and specifications.
• Assist in Analog, mixed-signal, and digital IC design.
• Participate in RTL coding and verification for digital ICs.
• Support design verification tasks.
• Conduct circuit simulations and analysis using Cadence, Synopsys, and Mentor Graphics tools.
• Assist layout engineers with floor planning.
• Analyze and debug silicon failures, suggesting design improvements.
• Contribute to the development of design methodologies to enhance efficiency.
• Document design work and test plans.
• Collaborate with cross-functional teams to ensure successful tape-out.

Requirements:

• Bachelor’s Degree in Electrical Engineering or equivalents.
• At least 2 years of relevant working experience.
• Understanding the IC development flow in advanced CMOS processes, including design, layout, and tape-out.
• Understanding the fundamental theories of digital or analog circuit design.
• Capability to generate inventive designs and circuit solutions tailored to fulfill customer needs.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Job Responsibilities:

• Identify project design hazards, construction risks, and constructability issues.
• Develop corresponding mitigation measures together with the project team.
• Chair regular risk mitigation meetings and training with clients and internal parties.
• Advise management on alternative safer and higher productivity construction methodologies.
• Review method statements and risk assessments for safety and construction compliance.
• Attend meetings related to construction progress, risks, etc.
• Any other duties as assigned by the Managements.

Job Requirements:

• Have reasonable exposure in safety and health for construction especially on transportation infrastructure projects in a similar nature
• Attended the Design for Safety (DfS) for Professional Course and passed the assessment or equivalent.
• A registered PE or Architect with a Practicing Certificate OR
• Minimum 10 years relevant experience in the design and the supervision of the construction of structures with at least 5 years in design which includes contributions to designs and writing specification
• Have a degree accepted by PE Board or Board of Architect and construction related degree accepted by Singapore Institute of Surveyors (SISV) and Society of Project Managers (SPM)
• Possess excellent leadership, planning, good management skills, interpersonal communication and negotiation skills
• Have experience in LTA projects have an advantage

Responsibilities

• Work as Senior Tankage Design Engineers to execute the Tankage Design Engineering of

the Project which includes design of Fixed Roof Tank / Floating Roof Tank as per API 650,

Low Pressure Tank as per API 620, Spherical Tank and Bullets as per ASME Section VIII &

Cryogenic Double Wall Tanks as per API 620 & API 625.

• Preparation, Review & Checking of Tankage Design Documents such as Design Calculation

for Tank, Finite Element Analysis, Tank Data Sheets, Tankage Material specification,

Tankage Fabrication Drawings & ensure Compliance to API 650, API 620, API 625, ASME

Sec VIII, AP 2000 and all Applicable Codes & Standards.

• Prepare all Tankage documents in accordance with project specification. Maintain Design

integrity and quality within the Project Engineering Team

• Preparing Engineering schedule and Engineering man hours estimation to meet project

requirements.

• Coordination with PMC and Construction Coordination.

• Participates in discipline and inter-discipline design check and screening meetings for

compatibility, completeness and correctness in works.

• FEED & Pre-Bid works which involves Feasibility study & MTO estimation works.

• Preparation of Technical Specification for Works and Technical Bid Evaluation

• Technical assistance to construction activities and attending to Site Queries.

• Preparation of Foundation Loading Data.

• Generate 2D construction drawings and data sheet.

• Preparation of purchase requisition for tank accessories such as roof seal, roof drain system,

aluminium dome roof & etc. Preparing technical bid evaluation for item purchased.

Checking vendor’s calculation & construction drawings.

• Checking of construction drawings. Preparation of bill of material for purchasing.

• Preparation of technical queries to client base on design deviation.

• To be proactive in creating a safe working environment for everyone and ensuring that HSE

in-house rules are observed at all times.

• To consider HSE aspects when planning and carrying out tasks to eliminate and reduce

HSE hazards, aspects and risks.

• Any additional Adhoc related work

Qualification

Preferably Bachelor of Engineering (Mechanical)

Experience

Preferably Min. 10 years’ experience in oil and gas.

Software Requirements

• Autocad

• Good proficiency in MS Excel , MS word

Code Knowledge

• API 650/ API 620

• ASME Section VIII D1 & D2

• ASME Section II Part A & D

• ASTM

• NFPA

Job Description & Requirements

• Responsible to the Principal Engineer, Piping for the preparation of design as per codes / standards and client’s specifications, requisitions for materials, equipment, valves, etc., and for the timely completion of each planned engineering activity assigned to him / her.
• Review of piping specification.
• Review piping stress analysis calculation.
• Review and finalize of piping routing, piping arrangement and support.
• Review design data for missing and / or ambiguities information.
• Reporting project progress to Principal Engineer, Piping on a weekly basis.
• Implementation of Engineering Procedure, drafting Standards and Quality Management.
• Preparation of proposals / estimations for equipment and tankage works.
• Review engineering calculation and technical specifications of storage tanks, pressure vessels and various mechanical equipment.
• Evaluate vendor’s bids and highlight deviations and omissions to purchasing for further clarifications with vendor.
• Perform any other responsibilities as directed by immediate supervisor.

Qualification & Experience generally required

• Bachelor Degree in Engineering.
• Min 8 years relevant working experience in Mechanical engineering in oil and gas sector or offshore sector.
• Know to use spring hanger in stress analysis.
• Proficient in Microsoft Office products, AutoCAD and Caesar ll Stress Analysis Software.
• Prefer to have at least 5 year of piping engineering related working experience.
• Prefer to have experience in Offshore/Shipyard project, Rig building/Ship building.
• Prefer to have experience in FPSO project, both topsides & marine.

• Create detailed designs and layouts for steel structures using CAD software (e.g., AutoCAD, Tekla, SolidWorks)
• Develop accurate structural drawings, including framing plans, connection details, and assembly drawings.
• Perform design calculations to ensure structural integrity, load-bearing capacity, and compliance with codes.
• Strong knowledge of steel structure design principles and software (e.g., STAAD.Pro, Tekla, SAP2000).
• Familiarity with construction materials, fabrication processes, and assembly techniques.