We are looking for a self-motivated candidate with expertise in high performance digital design, DSP and mixed signal modeling join our cryogenic CMOS-based quantum control project. This candidate will work closely with our digital and analog design team as well as with the local physics and material designers to develop low-power, high fidelity and highly scalable control and read-out SoC for superconducting qubit-based quantum computing applications.
Job Description:
· Digital IC Design and system-level exploration:
o Lead and contribute to co-optimization between on-chip memory and DSP design and analog front-end (i.e. DAC, BPF, Mixer, LNA and ADC) to ensure high quantum control/readout as well as to optimize power consumption per channel
o Emphasize system-level perspective in the design process, considering overall system architecture and functionality
o Apply a deep understanding of cryogenic temperature effects on digital ICs and implement design strategies for optimal performance in low-temperature environments
o RTL implementation for custom circuit design using Verilog/SystemVerilog with focus on DDS, Filter and Error Correction Code
· Simulation, Verification, and Implementation:
o Conduct thorough simulation and verification of mixed signal designs to validate quantum control fidelity and digital-analog interface throughput
o Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration
o Perform timing analysis and collaborate with the team to optimize designs for timing closure
- Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II
- Collaborate closely with cross-functional teams, including hardware and software engineers, to seamlessly integrate digital ICs into the overall system architecture
- Prepare detailed design documentation, including specifications, test plans, and reports
- Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues
- Bring creative and innovative solutions to design challenges. Stay abreast of industry trends and emerging technologies
- Test and verify fabricated chip using FPGA and other lab equipment such as logic analyzer and oscilloscope
Requirements: Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.
