UWCSEA Dover has a vacancy for an Art Technician from May 2024. Reporting to the Heads of Art, the successful incumbent will support the Art department and teachers with inventory and the creation and delivery of curriculum needs and materials.

Main Responsibilities

• Preparation of materials and provide classroom support for Teachers (delivery of iPad trolley, inventory and restocking of classroom supplies etc.).
• Assist in classroom routines and curriculum such as mounting/framing and hanging of artwork in the College, including annual Art exhibitions, GCSE exams, College displays etc.
• Conduct and maintain storeroom supply inventory.
• Assist students with technical constructions (i.e. general wood cutting).
• Work with a variety of common workshop tools and maintain the inventory, operation and proper storage of art tools (i.e. ceramics kiln, 3d printer, laser cutter etc. *Training for these tools can be provided.).
• Attend to any other duties as assigned.

Person Specifications

• Minimum Diploma in any related discipline with 2 years of experience.
• Relevant experience as a school art technician is desirable but will consider someone who has a good work history.
• Good initiative, self-management and communication skills.
• Ability to use basic woodcutting tools (i.e. cutting plywood down to standardised sizes)
• Knowledge of laser cutter, 3D printer, ceramics kiln is highly desirable, but some training can be provided.
• Ability to stretch canvas on frames.
• Ability to work independently and as part of a team.
• Approachable, friendly, and willing to assist in problem-solving.
• Able to manage time efficiently and prioritise tasks in the department.
• Physically fit to carry and handle artworks and materials (i.e. 10kg bags of clay).

Application

Apply via our portal by Tuesday, 2 April 2024 at 11:59pm Singapore Time.

The UWC Mission is to make education a force to unite people, nations and culture for peace and a sustainable future. We are committed to creating a community in which all members feel safe and secure, and know that their authentic selves and individual differences are accepted with respect and care. At UWCSEA, we acknowledge that diversity, equity, inclusion and justice (DEIJ) is an ongoing and evolving process and strive to create and sustain a sense of belonging for all members of our community, past, present and future. All qualified applicants, including those who identify as a part of marginalized group(s) and individuals with (dis)abilities are all encouraged to apply. Our school is committed to safeguarding and promoting the welfare of all the students in our care and expects all applicants to share this commitment. We follow safe recruitment practices and all appointments are subject to interview, satisfactory references, identity and criminal record checks.

Cognita, in partnership with Brighton College, is seeking an inspirational Teacher of Art (Senior School) to start in August 2024. The successful candidate will take a lead on all aspects of the art provision at Key Stage 3 in their first year in post, as Brighton College (Singapore) expands from a first-class Prep School to one of the region’s leading all-through schools (from Pre-Nursery to Year 13).

In August 2024, the Senior School at Brighton College (Singapore) will open with Years 7, 8 and 9. The successful candidate will teach across these three Senior School year groups in their first year, whilst also demonstrating an enthusiasm for teaching art to some Key Stage 2 year groups in the Prep School. The successful candidate will be able to teach art to GCSE/IGCSE and A-level as the Senior School grows, and should be able to demonstrate a strong track record of delivering top academic results in public exams in previous roles.

This is an exciting opportunity for an educationalist to help shape the development of a secondary curriculum that will provide a springboard for pupils to go on to some of the most competitive Art Foundation courses and leading universities. Once in role, the Teacher of Art will be instrumental in ensuring that the art provision aligns with the Brighton College commitment to building a world-class academic institution, distinctive in its own right, but with the Brighton College DNA at its core.

The position of Teacher of Art represents a career-defining, professional challenge for a candidate who is excited by the opportunity of growing a love of art in young people. As with all Brighton College teaching posts, the successful candidate will share our aim of developing well-educated, respectful, and curious young men and women ready to take a full, active and positive role in the world.

Key Responsibilities

• Take responsibility for the teaching, progress and attainment of all pupils in art in Years 7 to 9 from August 2024, and in all other senior year groups in the following years.
• Take responsibility for the teaching, progress and attainment of some Key Stage 2 year groups from August 2024, preparing the pupils for Senior School studies in art.
• Demonstrate the experience and ability to teach art at IGCSE/GCSE and A-level.
• Lead on all aspects of art curriculum planning and delivery, including preparation for the first IGCSE Year 10 cohort starting in August 2025.
• Promote excellence, creativity and innovation in all areas of the art curriculum.
• Demonstrate commitment to continuous professional development.
• Lead on all aspects of assessment, tracking and reporting for art.
• Act as an outstanding classroom practitioner, with the ability to lead by example.
• Devise and implement rigorous self-evaluation processes.
• Devise and oversee the department’s extension and enrichment programme.
• Demonstrate the experience and expertise needed to support pupils in future years with applications for competitive Art Foundation courses and to leading universities.
• Ensure pupils have opportunities to prepare for, and participate in, global creative arts competitions, providing appropriate stretch and challenge.
• Work closely with the Heads of EAL and AEN to develop pathways for pupils requiring additional support.
• Develop the required curriculum and department documentation, both for current and prospective parents.
• Organise regular exhibitions of pupil artwork.
• Contribute to the highest standards of safeguarding and to the school’s pastoral system, acting as a tutor for a Senior School year group.
• Contribute to the co-curricular life of the school.
• Any other reasonable management request.

Qualifications and Experience

• Bachelor’s degree in a relevant subject, with PGCE or equivalent.
• Expert knowledge or experience of successfully delivering GCSEs/IGCSEs and A-level.
• International experience (preferred but not essential)
• Exemplifies the Brighton College (Singapore) values of Curiosity, Confidence and Kindness.
• An international outlook and understanding of working in diverse environments.

SAFEGUARDING AND EQUAL OPPORTUNITIES

Brighton College is committed to safeguarding and promoting the welfare of children and young people and expects all staff and volunteers to share this commitment. Any offer of employment will be subject to an enhanced DBS disclosure, / international Police checks, the receipt of satisfactory references, the College’s pre-employment medical question, relevant original ID documentation and examination certificates. The College understands that a robust, fair and transparent recruitment and selection policy plays a central role in achieving this aim.

The College is committed to ensuring that the recruitment and selection of staff is conducted in a manner that is systematic, efficient and effective and promotes equality of opportunity.

The College reserves the right to appoint a candidate to the role in advance of any deadline date, in the event that a suitable candidate can be appointed.

© Brighton College (Singapore) Pte Ltd

CPE Registration Number: 201904884D

Job Purpose:

The Art Teacher is responsible for developing each child interest in arts and the ability to express their artistic ability and creativity, to acquire knowledge and aesthetic understanding, to nurture and develop talents.

Job Responsibility:

• Prepare course materials and execute planned art curriculum lessons in group settings.
• Educate and nurture child to express artistic ability, creativity through principles of art and techniques.
• Demonstrate art techniques in activities including drawing and painting.
• Provide guidance by which children develop aesthetic concepts and appreciations.
• Guide and explain to children on proper care and use of art materials and tools.
• Adopt supportive classroom approach which facilitates positive learning and development.
• Encourage children to express their own personalities and thoughts through creative process.
• Evaluate each child’s performance and growth in knowledge and aesthetic understandings.
• Provide quality feedback on child’s development progress.
• Participate in campus events including parent meeting sessions and festive events.
• Perform any other duties and responsibilities as assigned by the Art Teacher (Supervisor).

Job Requirement:

• Possess Diploma or Bachelor degree in Arts or equivalent.
• Prior experience working in classroom setting is an added advantage.
• Candidates who are innovative, highly driven and take initiative are encouraged to apply.
• Passionate in engaging, teaching and developing children.
• Good communication skills and is bilingual in both English and Mandarin to liase with Mandarin speaking stakeholders

Looking forward on your resume. Please drop your resume to [email protected].

Regret to inform you that only shortlisted candidates will be notified.

Responsibilities

• Responsible for development of new products and product improvements
• Responsible in performing the whole cycle of product design
• Responsible for designing and devleoping of quality product and ensuring manufacturability with other engineering functions involved in product development.
• Responsible in ensuring product designs are validated per customer requirements, respecting international industry standards

Requirements

• Min Degree in Mechanical Engineering, Manufacturing or other relevant discipline
• Min 3 years of working experience in Product Design Development
• Proficient with Pro-Engineer/ CREO/ANSYS/ Autocad

Please kindly email your resume in Ms Word to [email protected]

We regret to inform that only shortlisted candidates would be notified.

Registration Number: R1328870

EA License No. 22C1026

Responsibilities

• Responsible for development of new products and product improvements
• Responsible in performing the whole cycle of product design
• Responsible for designing and devleoping of quality product and ensuring manufacturability with other engineering functions involved in product development.
• Responsible in ensuring product designs are validated per customer requirements, respecting international industry standards

Requirements

• Min Degree in Mechanical Engineering, Manufacturing or other relevant discipline
• Min 3 years of working experience in Product Design Development
• Proficient with Pro-Engineer/ CREO/ANSYS/ Autocad

Please kindly email your resume in Ms Word to [email protected]

We regret to inform that only shortlisted candidates would be notified.

Registration Number: R1328870

EA License No. 22C1026

Responsibilities

• Responsible for designing and developing software for automated semi-conductor process equipment.
• Responsible for improving equipment performance through CIPs and other development initiatives
• Responsible for supporting field work to upgrade and resolve customer issues.

Requirements

• Min Diploma in Electrical & Electronics Engineering/Computer Studies or equivalent.
• Min 5 years of working experience in programming on Windows (XP and above) environment.
• Experience in C++, VC++, MFC, SQL, OOP, using Servo, Stepper Motion Controller, Analog Device and High Speed I/O
• Knowledge in developing multi-threaded control software, SEMI SECS/ GEM equipment connectivity standard and Software Development Life Cycle.

Please kindly email your resume in Ms Word to [email protected]

We regret to inform that only shortlisted candidates would be notified.

Registration Number: R1328870

EA License No. 22C1026

• Prepare work schedule.
• Prepare P/O or W/O for suppliers and tradesmen.
• Liaise with clients, suppliers and tradesmen for delivery and commencement of work.
• Monitor site progress and inform sales personnel and clients accordingly.
• Ensure quality of work is done according to design provided by sales personnel.
• To co-ordinate touch-up or rectification works, if any.
• To ensure project is completed on time according to work schedule.
• Ensure proper housekeeping on site.

Role and Responsibilities:

• Mixed-Signal IC (MEMS Interface) Design Engineer will be responsible for the design and development of capacitive and/or piezoelectric MEMS interface ASICs, including the required amplifiers, ADCs, filters and control logic, with characteristic high impedance inputs, ultra low power, low noise circuits etc .
• The responsibility of the Senior Mixed-Signal IC Design Engineer includes scheduling, design, simulation and layout of mixed-signal circuit blocks, including pre- and post-silicon verification

Requirements:

• Minimum BSEE with hands-on experience in IC Design flow.
• Familiarity with modern EDA tools such as Cadence, Mentor, Synopsys etc.
• Have working knowledge in analog building blocks such as bandgap reference, LDO, amplifiers, low noise amplifiers
• Understanding of ADC topologies eg Delta-Sigma, SAR, flash, integrating etc … advantageous
• A good team player with good communication skills
• Enthusiastic and independent worker.
• Willing to work in Tampines

The Education Consultant serve as the point of contact between Tree Art and prospective customers. The incumbent identifies and educate prospective customers on the Company’s course curriculum and supports customers by providing information and assistance with closing.

Main Duties:

• Actively seek, follow up and close on sales leads.
• Engage in effective sales pitch through familiarising with Tree Art curriculum and programme.
• Promote Tree Art courses, introduce and explain curriculum information to prospective customers.
• Identify and recommend on course curriculum that are tailored to customer’s needs and objectives.
• Liase closely with customers to address all course inquiries (ie; walk-in/online platforms) with closure.
• Coordinate with Centre Manager to ensure smooth process for customer registration and enrolment.
• Collect and review quality feedback from customers to improve sales.
• Responsible for administrative duties including maintaining database records and sales data analysis.
• Perform any other duties and responsibilities as assigned by the Centre Manager.

Job Specification:

• Possess at least diploma in any field.
• Fresh graduates who are pro-active and sales driven are welcome to apply.
• Prior experience working in sales is an added advantage.
• Good communication skills and is bilingual in both English and Mandarin to liase with Mandarin speaking stakeholders.

Job Description & Requirements

· Manage day to day operations and ensure smooth running of Tree Art campus.

· Proactively engage customers and build good rapport through understanding of students and their progress development.

· Engage in effective sales pitch through familiarising with Tree Art curriculum and programme.

· Support management in planning and executing strategies to increase sales.

· Plan, organise and communicate to customers on the various programme and campus events.

· Serve as customer’s main point of contact and manage communication platforms.

· Responsible for customer enquiries, student enrolment and post-sales services.

· Coordinate class schedule and arrange for replacement teachers when necessary.

· Monitor student attendance and follow up to arrange for makeup lesson.

· Perform administrative duties including maintaining ERP, student records and tracking withdrawals.

· Share expertise and provide guidance to direct report.

· Motivate and work as a team in the achievement of service excellence and centre targets.

· Liaise with landlord on updates.

· Perform any other duties and responsibilities as assigned by the Operations Director.

Working Hours (43 hours per work week):

Mon : off
Tuesday - Friday : 1.30pm - 7.30pm
Saturday and Sunday: 9.00am - 7.30pm

Job Purpose:

The Art Teacher is responsible for developing each child interest in arts and the ability to express their artistic ability and creativity, to acquire knowledge and aesthetic understanding, to nurture and develop talents.

Job Responsibility:

• Prepare course materials and execute planned art curriculum lessons in group settings.
• Educate and nurture child to express artistic ability, creativity through principles of art and techniques.
• Demonstrate art techniques in activities including drawing and painting.
• Provide guidance by which children develop aesthetic concepts and appreciations.
• Guide and explain to children on proper care and use of art materials and tools.
• Adopt supportive classroom approach which facilitates positive learning and development.
• Encourage children to express their own personalities and thoughts through creative process.
• Evaluate each child’s performance and growth in knowledge and aesthetic understandings.
• Provide quality feedback on child’s development progress.
• Participate in campus events including parent meeting sessions and festive events.
• Perform any other duties and responsibilities as assigned by the Art Teacher (Supervisor).

Job Requirement:

• Possess Diploma or Bachelor degree in Arts or equivalent.
• Prior experience working in classroom setting is an added advantage.
• Candidates who are innovative, highly driven and take initiative are encouraged to apply.
• Passionate in engaging, teaching and developing children.
• Good communication skills and is bilingual in both English and Mandarin to liase with Mandarin speaking stakeholders

Looking forward on your resume. Please drop your resume to [email protected].

Regret to inform you that only shortlisted candidates will be notified.

Job Purpose and Key Accountabilities:

As a Management Trainee, your main goal will be to learn and master various aspects of the company's operations, including but not limited to operations management, human resources management, team leadership, decision-making, and problem-solving. Through this training program, you will acquire the necessary skills and knowledge to prepare for future senior management positions.

Key Accountabilities:

1. Continuously learn and understand the specific business operations and management strategies of the company.
2. Participate in and lead team projects, enhancing teamwork and leadership.
3. Effectively manage and execute projects in a multitasking and high-pressure environment, with a results-oriented approach.
4. Solve problems encountered in work, formulate and implement solutions, emphasizing replicable processes.
5. Embrace change, continuously improve your skills and knowledge, and break through your own capability boundaries.

Main Duties and Responsibilities:

• Participate in the company's daily operations and management activities, learning the company's business processes and strategies.
• Assume a leadership role in projects, effectively distribute tasks and manage progress, ensuring smooth completion of projects.
• Think independently when encountering problems, propose and implement solutions, and conduct a review after problem resolution.
• Accept feedback from superiors and colleagues, continuously improve your skills and knowledge, and maintain positive energy with an open mindset to change.
• Enhance your professional knowledge and skills by participating in the company's training and learning activities and continuously learning.

Job Specification:

• Education: Fresh graduates from NUS/NTU/SMU in Singapore or those with one to two years of work experience. Bachelor's or master's degree in business management, education, psychology, or other related fields.
• Skills: Leadership and teamwork abilities, problem-solving and decision-making capabilities, project management skills.
• Personal Characteristics: High self-drive, leadership, adaptability, resilience.
• Career Goals: Passionate about education and training, looking forward to long-term development in the company, willing to take up a management position after completing the training.
• Others: Deep understanding of the education and training market in Singapore, familiar with basic information technology and software applications.

Working Hours (43 hours per work week):

Mon : off

Tuesday - Friday : 1.30pm - 7.30pm

Saturday and Sunday: 9.00am - 7.30pm

Responsibilities:

• Manage and support the interior design development and coordination process throughout the design and documentation phases.
• Manage the execution of interior works from tender till completion and handover
• Monitor to ensure resolution of design and technical coordination issues at site
• Review of Contractors’ submissions, work schedules, materials samples, shop drawings etc.
• Conduct site & factory visits, monitoring of quality of on and off-site fabrication
• Monitor and report of interior works progress and qualities, to ensure delivery timeline and workmanship

Requirements:

• Degree in Interior Architecture / Architecture or any related field
• At least 6 years of relevant experience in Interior Design & Site Execution, preferably with premium residential, offices, hotels experiences
• Self-driven, and able to work independently.
• Ability to multi-task and to work under pressure.
• Excellent problem-solving skill.
• Strong organizational, communication and interpersonal skill.
• Proficient in Project Management Programs, AutoCAD, SketchUp, 3D Max, Illustrator or other design programs, Microsoft Excel, Word, etc.

Meet the Team

The IoT Digital team is a state-of-art IC design team focused on producing world-class Wireless MCU SoCs. The architecture specification, design, verification, and implementation of the Wireless MCU SoCs is the responsibility of the IoT Digital team. These SoCs include an embedded CPU system with analog and digital peripherals, advanced security, state-of-the-art power management, and best-in-class radios to support a wide range of wireless IoT applications and standards.

Responsibilities

The chosen candidate will contribute to, and manage a team for, the development of architecture, microarchitecture, and design of complex, low power, Wireless SoCs. These SoC devices are multi-core, multi-threaded processor subsystems with multi-level cache, capable of supporting multiple wireless protocols and application functionality, such as sensor hub, AI /ML, while meeting best-in-class power and performance targets. The Chip Design lead will define architectures with embedded multi-core, multi-threaded processor subsystems, AI accelerators, bus interconnect, memory architecture and multi-level caches to satisfy performance and throughput requirements. This will include RISC-V, ARM or proprietary processor designs, high-speed interfaces for off-chip memories, integration of wireless systems, power management, and mixed signal IP. The candidate would be responsible for the leading a project through the entire product development process.

• Lead the development and execution of Wireless SoC’s from definition, through execution, and into production
• Definition and Planning
  Coordinate with the product marketing teams to develop the SoC requirements. Provide the necessary design collateral to support the product approval gates.
  Develop and maintain the SoC architecture or technical specification to meet the product requirements, with a key goal to maximize IP reuse.
  Develop the design schedule, including milestones and resource requirements. Coordinate with cross functional teams (such as software) on dependencies.
• Project Execution
  Coordinate with global design functional leads (RF, baseband, verification, etc) to track execution, triage issues, and perform prudent escalation.
  Represent the design community to provide succinct weekly status and attend the cross functional meeting. Drive design action items to closure.
  Perform SoC Design Integration and maintain design collateral such as documentation, register libraries, and pinouts delivered to cross functional teams.
  Follow established quality procedures and processes to achieve first tapeout.
• Validation to Production
  Actively support the validation and product test teams during silicon bringup, validation, characterization, and qualification.
  Triage, track, and resolve issues reported during silicon evaluation. Execute a metal or full layer revision, if necessary

Skills You Will Need

Minimum Qualifications:

• B.Tech/M.Tech in related branches of electronics and computer science with a minimum of 10 years of related experience.
• Capable of leading complex IP, SOC development projects execution. Experience coordinating with contractors a plus.
• Top-down planning and execution of SOC projects.
• Experience in full-chip development cycle
• Able to build strong technical team.
• Hands-on experience in architecture, micro-architecture, digital design processes
• Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI
• Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN, etc.
• Knowledge of processors like RISC-V and ARM processors
• Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure
• Knowledge of DFT including Scan, ATPG, MBIST
• Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)
• Knowledge of hardware accelerators
• Knowledge of Verilog and System Verilog
• Knowledge of scripting languages like Perl, Python, Tcl, shell

Benefits & Perks:

You can look forward to the following benefits:

• Employee Stock Purchase Program (ESPP)
• Medical and dental insurance coverage including spouse and child(ren)
• Bi yearly health screening and flu vaccination
• Office location is above Tai Seng MRT station

About the Team

The Digital Subsystems team is responsible for the research and development of digital architectures and IPs from concept to production. We develop compute engines (AI/ML), processors (RISC-V), accelerators, peripherals and system IP. Our activities include advanced research & development, high-level modeling, architecture, RTL design, timing/power/area optimization, formal and UVM verification within an automated framework. We value innovation, simplicity, quality, and smart development processes within a highly collaborative and learning-driven team.

What we’re looking for:
The Verification Lead will be responsible for technical leadership, direction-setting and significant hands-on contribution of advanced digital verification projects. The lead will have direct responsibility for the planning and execution of methodology and flows to be employed in the execution of verification projects. The lead will directly supervise the technical activities of verification projects such as test planning, execution, and reviews at both IP and system-levels. Included is communicating and synchronizing methodology and test development with verification leads and engineers at other sites. The lead is also expected to provide technical coaching and mentoring to team members on verification approaches, languages, and tools/methodologies.

Skills you’ll need:

• Provide technical leadership for a team of verification engineers
• Generate and execute verification plan based on specifications
• Architect and implement testbenches using UVM-based constrained-random
• Utilize architectural models to verify functionality of digital IP
• Develop integration and reuse guidelines for IP integration
• Coverage definition, implementation, and analysis
• Mentor junior engineers
• Support IC teams in integration and use of IPs
• Develop and improve flows and methodologies for efficient and high-quality development
• Skill development and training on modern verification techniques such as formal

Required Experience & Skills:

• Technical Team leadership and project execution ownership
  Ability to plan, track and manage a complex verification project comprising of a team of engineers
  Ability to mitigate unforeseen obstacles and maintain on-time execution to meet project schedules
  Technical leadership and mentorship
• Extensive experience with implementation of UVM testbenches:
  Verification component design with emphasis on decoupled stimulus and checking, robust random stimulus generation and reuse
  Reuse of IP-level testbenches in subsystem and system-level verification
  Assertion-based verification
• Ability to define and specify requirements for verification-related flows including:
  Simulation control and coverage
  Regression deployment and coverage collection
• Experience with EDA simulation tools

Preferred Experience & Skills (any of the below):

• Experience in deploying and maintaining formal verification applications for system-level connectivity verification.
• Experience in deploying and maintain formal property verification at an IP-level for interface protocol and internal functional verification.
• Experience in developing and deploying executable and reusable test plans and tracking their closure through regression
• Experience in verification of microprocessors
  Developing and debugging assertions with formal property verification for interface verification and/or internal processor operation
  Experience with processor debug techniques and design including test interfaces, debug and trace implementation and general debug infrastructure
  Experience developing and maintaining software toolchain and infrastructure to facilitate software testing of processor implementations.

​

Benefits & Perks:

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

• Employee Stock Purchase Program (ESPP)
• Medical and dental insurance coverage including spouse and child(ren)
• Bi yearly health screening and flu vaccination
• Office location is above Tai Seng MRT station

Key Responsibilities:

• Development of Analog/Mixed-Signal circuits from specifications to prototypes.
• System-level analysis and evaluation, full-chip architecture design, analysis, modeling, simulation, and integration.
• Schematic entry, corner simulation, layout consideration, and post-layout simulation.
• Work closely with the layout engineer to conduct the physical implementation (layout) and chip floor planning.
• Responsible for post-layout extraction and parasitic analysis.
• Able to work with other designers, Chip Architects, and layout engineers to achieve full-chip integration, place and route, top-level verification, and tape out.

Requirements:

• Ph.D./Master/Degree in Electrical Engineering or Microelectronics with excellent technical background in Analog /Mixed-Signal IC design
• Min. 8 years of experience in CMOS Analog IC design and simulation
• Good design experience in Analog IC design involving two or more of the following blocks: low noise pre-amplifier (low offset, high CMRR, high PSRR and bandwidth up to 600MHz), CMOS Gigahertz Oscillator, switched capacitor circuit, LDO, Differential Amplifier, comparator, Opamp, TIA, and Bandgap Reference and high-frequency full-wave rectifier, etc.
• Good design knowledge in ESD and Latch-Up.
• Experience in isolator devices (capacitive-coupler or optical-coupler) and photodetector-associated circuits will be an added advantage.
• Experience with sigma-delta modulators and IO drivers will be an added advantage.
• Good working knowledge of relevant analog IC design and simulation tools (Spice or its equivalent)
• Basic understanding and can develop simple design-related scripts with some common script languages, such as perl, Tcl, matlab or cadence skill etc.
• A team player with good communication skills.
• Able to work independently, flexibly, and creatively.

We are looking for a self-motivated candidate with expertise in high performance digital design, DSP and mixed signal modeling join our cryogenic CMOS-based quantum control project. This candidate will work closely with our digital and analog design team as well as with the local physics and material designers to develop low-power, high fidelity and highly scalable control and read-out SoC for superconducting qubit-based quantum computing applications.

Job Description:

· Digital IC Design and system-level exploration:

o Lead and contribute to co-optimization between on-chip memory and DSP design and analog front-end (i.e. DAC, BPF, Mixer, LNA and ADC) to ensure high quantum control/readout as well as to optimize power consumption per channel

o Emphasize system-level perspective in the design process, considering overall system architecture and functionality

o Apply a deep understanding of cryogenic temperature effects on digital ICs and implement design strategies for optimal performance in low-temperature environments

o RTL implementation for custom circuit design using Verilog/SystemVerilog with focus on DDS, Filter and Error Correction Code

· Simulation, Verification, and Implementation:

o Conduct thorough simulation and verification of mixed signal designs to validate quantum control fidelity and digital-analog interface throughput

o Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration

o Perform timing analysis and collaborate with the team to optimize designs for timing closure

• Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II
• Collaborate closely with cross-functional teams, including hardware and software engineers, to seamlessly integrate digital ICs into the overall system architecture
• Prepare detailed design documentation, including specifications, test plans, and reports
• Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues
• Bring creative and innovative solutions to design challenges. Stay abreast of industry trends and emerging technologies
• Test and verify fabricated chip using FPGA and other lab equipment such as logic analyzer and oscilloscope

Requirements: Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

Key Responsibilities:

• Working on ASIC digital design, including RTL coding based on Verilog, simulation, RTL and gate-level verification, code coverage, testbench development, logic synthesis, and design documentation.

Key Requirements:

• Master/Degree in Electrical Engineering with 5 years of ASIC design experience preferred.
• Familiar with ASIC design flow
• Experience in RTL coding based on Verilog. Familiar with the digital simulation debugging environment.
• Familiar with UNIX/Linux environment and scripting
• A team player with good communication skills
• Able to work independently, flexibly, and creatively.
• Strong analytical and problem solving

Key Responsibilities:

• Working on ASIC digital design, including RTL coding based on Verilog, simulation, RTL and gate-level verification, code coverage, testbench development, logic synthesis, and design documentation.

Key Requirements:

• Master/Degree in Electrical Engineering with 8 years of ASIC design experience preferred.
• Familiar with ASIC design flow
• Experience in RTL coding based on Verilog. Familiar with the digital simulation debugging environment.
• Familiar with UNIX/Linux environment and scripting
• A team player with good communication skills
• Able to work independently, flexibly, and creatively.
• Strong analytical and problem solving

Key Responsibilities:

• Development of Analog/Mixed-Signal circuits from specifications to prototypes.
• System-level analysis and evaluation, full-chip architecture design, analysis, modeling, simulation, and integration.
• Schematic entry, corner simulation, layout consideration, and post-layout simulation.
• Work closely with the layout engineer to conduct the physical implementation (layout) and chip floor planning.
• Responsible for post-layout extraction and parasitic analysis.
• Able to work with other designers, Chip Architects, and layout engineers to achieve full-chip integration, place and route, top-level verification, and tape out.

Requirements:

• Ph.D./Master/Degree in Electrical Engineering or Microelectronics with excellent technical background in Analog /Mixed-Signal IC design
• Min. 3 years of experience in CMOS Analog IC design and simulation
• Good design experience in Analog IC design involving two or more of the following blocks: low noise pre-amplifier (low offset, high CMRR, high PSRR and bandwidth up to 600MHz), CMOS Gigahertz Oscillator, switched capacitor circuit, LDO, Differential Amplifier, comparator, Opamp, TIA, and Bandgap Reference and high-frequency full-wave rectifier, etc.
• Good design knowledge in ESD and Latch-Up.
• Experience in isolator devices (capacitive-coupler or optical-coupler) and photodetector-associated circuits will be an added advantage.
• Experience with sigma-delta modulators and IO drivers will be an added advantage.
• Good working knowledge of relevant analog IC design and simulation tools (Spice or its equivalent)
• Basic understanding and can develop simple design-related scripts with some common script languages, such as perl, Tcl, matlab or cadence skill etc.
• A team player with good communication skills.
• Able to work independently, flexibly, and creatively.

We are looking for a candidate for high-speed analog and mixed-signal integrated circuit design. This candidate will contribute to the development of high-speed silicon photonics transceiver for next generation wireline communication system. This requires the candidate to work closely with the optics team on the electro/optical co-design as well as system integration and validation.

• Perform system level analysis and design, to derive circuit-level design specifications.
• Design and tapeout ICs which include state-of-the-art circuit blocks e.g. analog-to-digital converter, equalizers (CTLE, DFE) as part of the high-speed data link system.
• Work together with team to investigate novel circuit/system solutions to create new inventions

Job Requirements

• Qualification & Field of Study: Minimum Bachelor’s degree and above in Electrical Engineering
• Min. Years of Experience: Minimum 2-years of transistor level analog circuit design experience

Other Requirements (e.g. Skills, Competencies)

• Good understanding of CMOS analog and mixed-signal IC design methodologies and successful tapeout experience
• Familiar with analog and mixed-signal IC design and verification flow
• Industry experience would be a plus
• Familiar with the IC test equipment such as oscilloscope, spectrum analyzer, etc.
• Good communication skills (both written and spoken)
• Able to generate high quality scientific publications and patents
• Team player, quick learner and self-driven

We are looking for a candidate for high-speed analog and mixed-signal integrated circuit design. This candidate will contribute to the development of high-speed silicon photonics transceiver for next generation wireline communication system. This requires the candidate to work closely with the optics team on the electro/optical co-design as well as system integration and validation.

• Perform system level analysis and design, to derive circuit-level design specifications.
• Design and tapeout ICs which include state-of-the-art circuit blocks e.g. analog-to-digital converter, equalizers (CTLE, DFE) as part of the high-speed data link system.
• Work together with team to investigate novel circuit/system solutions to create new inventions

Job Requirements

• Qualification & Field of Study: Minimum Bachelor’s degree and above in Electrical Engineering
• Min. Years of Experience: Minimum 2-years of transistor level analog circuit design experience

Other Requirements (e.g. Skills, Competencies)

• Good understanding of CMOS analog and mixed-signal IC design methodologies and successful tapeout experience
• Familiar with analog and mixed-signal IC design and verification flow
• Industry experience would be a plus
• Familiar with the IC test equipment such as oscilloscope, spectrum analyzer, etc.
• Good communication skills (both written and spoken)
• Able to generate high quality scientific publications and patents
• Team player, quick learner and self-driven

We are looking for a self-motivated candidate with expertise in high performance digital design, DSP and mixed signal modeling join our cryogenic CMOS-based quantum control project. This candidate will work closely with our digital and analog design team as well as with the local physics and material designers to develop low-power, high fidelity and highly scalable control and read-out SoC for superconducting qubit-based quantum computing applications.

Job Description:

· Digital IC Design and system-level exploration:

o Lead and contribute to co-optimization between on-chip memory and DSP design and analog front-end (i.e. DAC, BPF, Mixer, LNA and ADC) to ensure high quantum control/readout as well as to optimize power consumption per channel

o Emphasize system-level perspective in the design process, considering overall system architecture and functionality

o Apply a deep understanding of cryogenic temperature effects on digital ICs and implement design strategies for optimal performance in low-temperature environments

o RTL implementation for custom circuit design using Verilog/SystemVerilog with focus on DDS, Filter and Error Correction Code

· Simulation, Verification, and Implementation:

o Conduct thorough simulation and verification of mixed signal designs to validate quantum control fidelity and digital-analog interface throughput

o Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration

o Perform timing analysis and collaborate with the team to optimize designs for timing closure

• Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II
• Collaborate closely with cross-functional teams, including hardware and software engineers, to seamlessly integrate digital ICs into the overall system architecture
• Prepare detailed design documentation, including specifications, test plans, and reports
• Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues
• Bring creative and innovative solutions to design challenges. Stay abreast of industry trends and emerging technologies
• Test and verify fabricated chip using FPGA and other lab equipment such as logic analyzer and oscilloscope

Requirements: Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

Key Responsibilities:

• Working on ASIC digital design, including RTL coding based on Verilog, simulation, RTL and gate-level verification, code coverage, testbench development, logic synthesis, and design documentation.

Key Requirements:

• Master/Degree in Electrical Engineering with 3 years of ASIC design.
• experience preferred.
• Familiar with ASIC design flow.
• Experience in RTL coding based on Verilog. Familiar with the digital simulation debugging environment.
• Familiar with UNIX/Linux environment and scripting.
• A team player with good communication skills.
• Able to work independently, flexibly, and creatively.
• Strong analytical and problem solving.

Key Responsibilities:

• Development of Analog/Mixed-Signal circuits from specifications to prototypes.
• System-Level analysis and evaluation, full-chip architecture design, analysis, modeling, simulation, and integration.
• Schematic entry, corner simulation, layout consideration, and post-layout simulation.
• Work closely with the layout engineer to conduct the physical implementation (layout) and chip floor planning.
• Responsible for post-layout extraction and parasitic analysis.
• Able to work with other designers, Chip Architects, and layout engineers to achieve full-chip integration, place and route, top-level verification, and tape out.

Requirements:

• Ph.D./Master/Degree in Electrical Engineering or Microelectronics with excellent technical background in Analog /Mixed-Signal IC design
• Min. 5 years of experience in CMOS Analog IC design and simulation
• Good design experience in Analog IC design involving two or more of the following blocks: low noise pre-amplifier (low offset, high CMRR, high PSRR and bandwidth up to 600MHz), CMOS Gigahertz Oscillator, switched capacitor circuit, LDO, Differential Amplifier, comparator, Opamp, TIA, and Bandgap Reference and high-frequency full-wave rectifier, etc.
• Good design knowledge in ESD and Latch-Up.
• Experience in isolator devices (capacitive-coupler or optical-coupler), Photodetector-associated circuits will be an added advantage.
• Experience with sigma-delta modulators and IO drivers will be an added advantage.
• Good working knowledge of relevant analog IC design and simulation tools (Spice or its equivalent)
• Basic understanding and can develop simple design-related scripts with some common script languages, such as perl, Tcl, matlab or cadence skill etc.
• A team player with good communication skills.
• Able to work independently, flexibly, and creatively.