We are looking for a self-motivated candidate with expertise in high performance digital design and system level architecture modeling to join our Heterogeneous System design team. This candidate will work closely with IME's advanced packing team and contribute to the exploration, optimization and development of multicore & multi-chip system using IME's heterogeneous integration platform.

Job Description:

Digital IC Design and system-level exploration:

• Contribute to the design and development of digital integrated circuits, ensuring they meet performance and functionality requirements.
• Emphasize a system-level perspective in the design process, considering overall system architecture and functionality.
• Incorporate Edge AI principles into digital IC designs, enabling efficient and intelligent processing at the edge of the network.
• RTL implementation for custom circuit design using Verilog/SystemVerilog
• Derive specs and implement necessary customized and highly efficient building blocks such as systolic array, data path controller, scheduler, integer and floating-point processing engine, FFT, etc which are frequency used in various computing architectures.

Simulation, Verification, and Implementation:

• Conduct thorough simulation and verification of digital designs to validate functionality and performance.
• Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration
• Perform timing analysis and collaborate with the team to optimize designs for timing closure.
• Contribute to power analysis activities and implement power-efficient design techniques.

Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II.

Prepare detailed design documentation, including specifications, test plans, and reports.

Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues.

Bring creative and innovative solutions to design challenges, staying abreast of industry trends and emerging technologies.

Requirements:

• Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

We are looking for a self-motivated candidate with expertise in high performance digital design and system level architecture modeling to join our Heterogeneous System design team. This candidate will work closely with IME's advanced packing team and contribute to the exploration, optimization and development of multicore & multi-chip system using IME's heterogeneous integration platform.

Job Description:

Digital IC Design and system-level exploration:

• Contribute to the design and development of digital integrated circuits, ensuring they meet performance and functionality requirements.
• Emphasize a system-level perspective in the design process, considering overall system architecture and functionality.
• Incorporate Edge AI principles into digital IC designs, enabling efficient and intelligent processing at the edge of the network.
• RTL implementation for custom circuit design using Verilog/SystemVerilog
• Derive specs and implement necessary customized and highly efficient building blocks such as systolic array, data path controller, scheduler, integer and floating-point processing engine, FFT, etc which are frequency used in various computing architectures.

Simulation, Verification, and Implementation:

• Conduct thorough simulation and verification of digital designs to validate functionality and performance.
• Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration
• Perform timing analysis and collaborate with the team to optimize designs for timing closure.
• Contribute to power analysis activities and implement power-efficient design techniques.

Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II.

Prepare detailed design documentation, including specifications, test plans, and reports.

Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues.

Bring creative and innovative solutions to design challenges, staying abreast of industry trends and emerging technologies.

Requirements:

• Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

Job Description:

- Perform Civil, Structural Analysis and Design (entry-level) to meet project specifications

- Coordination and Liaise with Clients, Authority and Other Consultants, Contractors on Projects

- Ensuring Good Project Documentation and Submission to Authority and Clients

- Attend Project Meeting and Perform Inspections on Designed Works

- Reporting to Senior Engineer

Job Requirements:

- Candidate must possess at least a Bachelor's Degree / Post-Graduate Diploma / Professional Degree in Engineering (Civil/ Structural) or equivalent, recognized by Professional Engineering Board of Singapore

- At least 1 Year (s) of working experience in the related field is required for this position

- Good Working Attitude, Self-Motivated, Positive Thinking, Independent, Discipline, Attention to Details and Ownership of Tasks

- Familiar with Local Design Standard and Code

- Knowledge of Design Software, e.g., STAAD Pro, Plaxis, AutoCAD will be added advantage

- Candidate with longer experience or qualifications will be considered for Senior Positions

Job Description:

- Perform Civil, Structural Analysis and Design to meet project specifications

- Coordination and Liaise with Clients, Authority and Other Consultants, Contractors on Projects

- Ensuring Good Project Documentation and Submission to Authority and Clients

- Attend Project Meeting and Perform Inspections on Designed Works

- To Lead and Mentor Junior Engineer in Performing Engineering Task

- Reporting to Principal Engineer / Management

Job Requirements:

- Candidate must possess at least a Master's Degree /Bachelor's Degree / Post-Graduate Diploma / Professional Degree in Engineering (Civil/ Structural) or equivalent, recognized by Professional Engineering Board of Singapore

- At least 4 Year (s) of working experience in the related field is required for this position

- Good Working Attitude, Self-Motivated, Positive Thinking, Independent, Discipline, Attention to Details and Ownership of Tasks

- Familiar with Local Design Standard and Code

- Knowledge of Design Software, e.g., STAAD Pro, Plaxis, AutoCAD will be added advantage

This is an opportunity to be a key player at a company with a great reputation in IoT semiconductor technology and growing business. We are looking for experienced/senior engineers to join our team in Singapore and be involved to develop the next generation IoT/AI chips based on a revolutionary architecture.

1. Work with team to define the design of WIFI/BT related modules.
2. Develop RTL design of one or more blocks, define RTL module partition, timing requirement etc.
3. Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process.
4. Assist with the development of company documentation and generation of patents.

Qualification

1. Master's degree in Electrical Engineering (or equivalent), with 5+ years’ industry experience.
2. Team player, with good problem solving and communication skills.
3. Proficiency in System Verilog for RTL logic design and verification.
4. Familiarity with the design of digital MAC/baseband/high-speed interface/CPU or DSP is a plus.
5. Experience in Architecture/Block definition for SOC system such as WiFi, Bluetooth and GNSS.
6. Experience in micro-architecture design, and RTL coding with Verilog, familiar with Cadence and Synopsis tools.
7. Experience in synthesis, with analysis of power, timing and area.
8. Review micro-architecture to meet specification requirements and perform Design Quality Check
9. Experience in RTL and gate level simulation, unit test, system test and EDA verification

At Mediatek’s Memory Design Automation team, we work seamlessly with worldwide memory design team to deliver high performance, low power and small area in-house memories design kits and design flows under advanced technology nodes. We are looking for candidate to join us as memory design automation engineer for the delivery of robust memory and development of Memory Compiler automation flow.

Responsibility

1. Responsible for cutting edge technology node’s SRAM compiler design and deliver best quality of design kit.
2. Seamlessly collaborate with SRAM design and layout team to achieve highest quality of design kit delivery.
3. Responsible for data analysis and platform development of memory usage big data.
4. Responsible for physical verification (DRC/ERC/LVS/ANT/PERC) on SRAM compiler.
5. Responsible for spice simulation on timing, power and noise on SRAM compiler.
6. Responsible for QA check and development on SRAM compiler.

Requirements

1. Bachelor or Master Degree in Electrical and Electronic Engineering or Computer Engineering or Computer Science.
2. Multi-task capability and strong self-driven characteristics to meet challenging schedule.
3. Proficient with Perl, Shell, Python, C/C++ languages, knowledge with AI machine learning algorithm and infrastructure is an added advantage.
4. Strong interpersonal skills to work with team members with multi-cultural environment
5. Knowledge of high performance, low power SRAM/ROM and VLSI design is an added advantage. Experience with EDA tools will be helpful.
6. Candidate with experience is preferable.

Location: One North, Singapore

Why MediaTek?

MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact. – Join us now!

Mediatek’s Memory Design Automation team is looking for fresh talent to join us as a modeling engineer for the development of behavioral, FPGA, timing and DFT simulation models. The role will be required to create, debug and optimize SRAM models for ASIC design flow.

The candidate must be a team player, able to communicate clearly and concisely to deliver quality work on time.

About the team:

The Mediatek’s Memory modelling team collaborates with the world-wide memory design teams to create and qualify front-end models for use in the ASIC design flow. Team members will also be expected to perform circuit design verification to ensure memory circuits robustness.

What you do:

• Develop and integrate automation code into existing memory compilers to generate models meant for ASIC design flow.
• Develop automation flow and scripts with Perl or Python.
• Execute EDA tools from vendors such as Synopsys, Mentor to verify models’ correctness.
• Stay up to date with current modeling standards and development to improve models and flows for better memory IP performance.
• Work with memory design, compiler team and DFT team and tool vendors to resolve model issues and find solutions.

What you bring:

• Must have a Bachelor’s degree or higher in Electrical Engineering, Electronics Engineering, or related discipline with at least 3 years of semiconductor industry experience.
• Have at least 3 years experience using Linux systems.
• Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must.
• Good understanding of liberty timing syntax.
• Good understanding of upf and system verilog.
• Knowledge and experience with EDA simulation tools such as VCS, NC is required
• Experience with EDA tools will be helpful:

o DFT: Logicvision, Tessent, Fastscan

o Synthesis: Design compiler, Genus

o Simulation tools:VCS, QuestaSim, NC

o STA tools such as PrimeTime

• Good scripting and flow automation skills, in Perl or Python.
• A team player, meticulous, able to work and learn independently are important attributes for this job.

Location: One North, Singapore

What you will do

• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Verification automation flow.

What you will bring

• Bachelor's/Master's Degree in EEE/Computer/IC design/equivalent.
• With min. of 8 years of relevant verification experiences.
• With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong experience and debugging ability on SystemVerilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell.
• Fast learner and a good team player.
• Candidates with more years of experience will be considered for a more senior role.

About the team

Our ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.

In MediaTek, we promote diversity and inclusiveness. Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!

Responsibilities:

• Manage and support the interior design development and coordination process throughout the design and documentation phases.
• Manage the execution of interior works from tender till completion and handover
• Monitor to ensure resolution of design and technical coordination issues at site
• Review of Contractors’ submissions, work schedules, materials samples, shop drawings etc.
• Conduct site & factory visits, monitoring of quality of on and off-site fabrication
• Monitor and report of interior works progress and qualities, to ensure delivery timeline and workmanship

Requirements:

• Degree in Interior Architecture / Architecture or any related field
• At least 6 years of relevant experience in Interior Design & Site Execution, preferably with premium residential, offices, hotels experiences
• Self-driven, and able to work independently.
• Ability to multi-task and to work under pressure.
• Excellent problem-solving skill.
• Strong organizational, communication and interpersonal skill.
• Proficient in Project Management Programs, AutoCAD, SketchUp, 3D Max, Illustrator or other design programs, Microsoft Excel, Word, etc.