Rules & Responsibilities

We are seeking a dynamic FIELD SUPERVISOR ( MA KET RESEARCH) with strong leadership abilities to join our team. We are a company with a commitment to innovation and excellence. If you're a creative and strategic marketer with a passion for driving results and the ability to inspire and lead a team, we want to hear from you. Candidates are required to be experienced in marketing for the Construction Sector with good existing network and contacts.

Job Description:

* Strong marketing & presentation preparations skillets.

* Build strong client relationships to maintain old business and acquire new customers in local market

* Maintain regular communication with clients to ensure that all of their needs are understood and addressed.

* Collaborate with various internal departments and consultants to ensure that they fulfill

Customers requests and focus on improving the customers’ experience.

* Resolve complaints and keep track of all processes that pertain to the client’s desires.

*Build and strengthen the relationship with consultants, contractors and developers.

* Collect and analyze data concerning consumer behavior to understand changing needs.

* Prepare quotations, tender compliances and marketing proposals.

* Other ad-hoc duties as assigned.

Compulsory Job Responsibility & Requirements:

1) Master's degree in marketing, Sociology, business, or related field.

2) Mandatory working day Monday to Saturday 9am to 9pm (3 hours over time)

3) At least 4 years related experience in Singapore building construction marketing site

.4) Must be work on weekends or public holidays for essential job

5) Someone willing to take hardship job

6) Knowledge of our industry and target audience is a plus.

7) Creative thinking and problem-solving abilities.

8) Proven experience in marketing roles, including leadership or marketing operations manager.

9) Budget planning and management skills.

10) Strong strategic thinking, communication, and leadership skil

11) Proficiency in digital marketing channels and tools

12) Excellent organizational skills and attention to detail. 13) Able to build and maintain good rapport with all internal and external stake holders including clients, consultants, contractors, developers and team members.

14) Experience and equipped with strong international contact bases e.g. Developers, Consultants, Contractors.

15) Excellent negotiation, communication and presentation skills.

See how you compare with other applican

Job Qualifications:

• Willingness to work in non-climate-controlled conditions (heat, cold, outdoors)
• Ability to lift heavy materials and equipment
• Willingness to work overtime
• Willing to work midnight shift
• Excellent customer service skills
• Min 3 Years relevant working experiences
• Secondary School / high school / diploma or equivalent
• Carpentry and renovation experience a plus

Job Responsibilities:

• Cut tiles and shape them properly to ensure they fit around obstacles and in tight corners and odd spaces using power and hand tools
• Form tile beds using concrete, plaster, mastic, cement, glue or mortar utilizing tools such as screeds, brushes and trowels
• Align tiles and straighten them with straightedges, levels and squares to ensure patterns are even and precise
• Cut, install, polish and surface granite and marble and ensure accuracy during the installation process for lasting results
• Prepare various surfaces for tiling with waterproofing material or lath and by cleaning the surfaces properly
• Create decorative wall and floor designs by laying and setting mosaic tiles in kitchens, bathrooms and living rooms
• Tap tiles into place carefully using tools to properly adhere tiles to the base, making sure not to break or damage tiles

Follow blueprints precisely and mark and measure surfaces that need to be tiled to determine how to go

Roles & Responsibilities

• Bricklaying
• Apply waterproofing
• Installation of panel
• Plastering and skimming
• Preparing construction sites, materials, and tools.
• Loading and unloading of materials, tools, and equipment.
• Removing debris, garbage, and dangerous materials from sites.
• Assembling and breaking down barricades, temporary structures, and scaffolding

A research position is available at the Singapore University of Technology and Design (SUTD). The research focuses on semantic communications, resource allocation, and edge AI.

Candidates with strong publication records in relevant areas are encouraged to apply. The candidate should have:

• Bachelor’s / Master's degree in computer science or related degree
• Strong publication record in top-tier IEEE conferences/journals
• Proficient in oral and written English

Kindly note that only shortlisted candidates will be notified.

Job Summary : We are seeking a versatile Accounts cum Admin Executive to join our team. This role combines administrative support with basic accounting tasks, providing an excellent opportunity for someone looking to develop skills in both areas. The Admin cum Account Assistant will play a crucial role in ensuring the smooth operation of our office financial processes and making it ideal for individuals who thrive in a fast-paced environment and enjoy multitasking .

Join our team as an Accounts & Admin Executive, a pivotal role reporting directly to the Accountant. This position primarily focuses on accounting responsibilities, encompassing 70% of the workload, while also involving 30% administrative tasks.The successful candidate will play a key role in maintaining accurate financial records, ensuring compliance, and contributing to the overall efficiency of our finance department.

Job Descriptions:

• Partake in full spectrum of AP and AR duties such as preparing and processing electronic transfers and payments, reimbursement of staff claims, generating sales invoices, preparing Statement of Accounts and following up on the overdue invoices;
• Assist in month-end closing and quarterly GST submission;
• Assist in annual statutory audit / corporate income tax filing;
• Liaise with external parties such as auditors, banks and vendors;
• Handle day-to-day office and admin duties like answering phone calls, mailing data entry, collect mails from letter boxes, purchase order, filling and etc;
• Administration work including ordering of stationery and pantry items, renewal of company insurance, renewal of electrical license, maintaining accurate historical records etc.
• Support internal stakeholders on travel desk management such as reservation of hotel rooms, air tickets and travel insurance;
• Maintain clean and organized documents - both paper and electronic files, keep records up to date;
  Any other ad-hoc duties assigned.

Requirements:Minimum a Degree in Finance/Accountancy/Banking / computer , or equivalent.
Minimum 3 years of accounting experiences.

Must exp with QuickBook

Meticulous and detailed oriented.
Proactive and possess positive attitude.
Able to work independently.
Written & spoken English and Tamil to communicate with parent company.
Proficient in Microsoft Office (e.g. Excel, Word).
Candidate with SAP Software knowledge will be an added advantage.
Candidate able to start within short notice will be an added advantage.

Key Responsibilities

• Fast development of analog IC physical designs, including layout drawing, DRC, LVS

• Layout extractions and analysis for IC designers

• Develop analog and/or digital library cells in various technologies (e.g. CMOS & SOI)

• Layout digital cells for various trade-offs (including speed, power, area, reliability)

• Layout analog circuits and IO circuits

• Characterize digital cell cells for timing and power analyses

• Construct test structures for validating various digital and analog cells

• Layout integration and optimization

• Advise IC designers for best layout practice

• Work with the IC design team to deliver IC physical designs

• Support the team lead for layout design integrations

Minimum Requirements

•Degree in electrical engineering or related field

• Strong experience in analog physical design, particularly bandgap, amplifier, comparator, LDO, current sensing, power switch, etc.

• Proficiency with industry-standard tools such as Cadence, Spectre, HSPICE, and Matlab

• Familiarity with CMOS, BiCMOS, and other process technologies

• Excellent problem-solving skills and ability to work in a fast-paced startup environment

• At least 3-year experience of analog layout design with at 2 IC product tapeouts.

• Some understanding of circuit analysis and implementation

• Strong expertise in power management including DC/DC converter design.

• Able to do design verifications

Responsibilities:

• Lead RTL design, simulation, and verification for company ASIC/SoC products, ensuring robustness.
• Integrate and validate IP blocks for seamless system functionality.
• Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs.
• Collaborate with backend team in RTL coding, implementation, and synthesis for successful tapeout.
• Create and maintain reusable IPs for AI/in-memory computing.
• Support Post-Si testing to ensure product functionality and quality.
• Mentor junior engineers to facilitate their professional growth.
• Contribute to design reviews for improved product performance and reliability.
• Stay current on RTL design methodologies for efficiency and quality.
• Collaborate with cross-functional teams for successful product development.

Requirements:

• Minimum Master in Electrical Engineering with 5 years of working experience with emphasis on RTL/SoC/digital design.
• Proficient in Verilog and SystemVerilog.
• Proficient in VCS, Verdi, or similar industry-standard tools.
• Skilled in pre-layout and post-layout simulation.
• Knowledgeable about the design flow and collaboration with backend teams.
• Familiar with AMBA APB and AXI protocols.
• Familiar with RISC/Arm or other core architectures.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

JOB DESCRIPTION:

• Tender estimation and costing.
• Quantity take-off, estimation, cost planning, subcontracting, Variation Orders and Final Accounts with Clients.
• To review progress of all on-going projects and preparation of monthly progress claim submissions to Clients; as well as evaluates and prepare Subcontractors’ claims.
• Undertaking duties/assignments as and when appropriately assigned by the HOD/Superior.

REQUIREMENTS:

• Degree in Structural / Civil Engineering or Quantity Surveying
• Minimum 3 years of relevant working experience in Tender and Estimating Works.
• Able to read and understand Drawings well.
• Extensive knowledge and experience in estimating construction projects.
• Knowledge of Structural Steel works will be an advantage.
• Knowledge of Standard Conditions of Contracts and Sub-contracts.
• High proficiency with Microsoft office software in Excel and Word.
• With good interpersonal and communication skills.
• Can work under pressure.

Note: Working hours; 8am-525pm (Mon-Fri); 8am-12noon (Alternate Saturday off)

We are seeking a motivated and innovative Post-Doctoral Research Fellow to conduct cutting-edge research in AI safety. The candidate will focus on curating data, aligning AI models, identifying gaps between academic research and industry practices, and developing tools to govern AI behavior. The position also requires regular publication in top-tier AI conferences and journals. This role offers the opportunity to contribute to the development of responsible and safe AI systems while working at the forefront of AI research.

Key Responsibilities:

1) Data Curation and Management: Collect, clean, and organize datasets relevant to AI safety research. Ensure data quality and accessibility for model training and evaluation.

2) Model Alignment and Development: Align AI models with safety objectives, ethical guidelines, and societal norms. Design and evaluate methods to prevent unsafe or unintended AI behavior.

3) Gap Analysis: Identify gaps between current AI safety research and industry practices. Propose actionable solutions and frameworks to address these gaps.

4) User Interviews and Research: Conduct interviews and surveys with stakeholders (users, developers, policymakers) to understand real-world challenges in AI safety. Integrate findings into research and tool development.

5) Tool Development: Develop practical tools, frameworks, or methodologies to govern and evaluate AI behavior. Prototype solutions that enhance AI interpretability, robustness, and compliance with ethical guidelines.

6) Research and Publication: Conduct high-quality, novel research in AI safety. Publish findings regularly in top-tier AI conferences and journals (e.g., NeurIPS, ICML, ICLR, AAAI, ACL).

Qualifications:

• Ph.D. in Computer Science, Artificial Intelligence, Machine Learning, or a related field.
• Demonstrated research experience in AI safety, ethical AI, alignment, or related areas.
• Strong programming skills in Python and experience with AI/ML frameworks (e.g., TensorFlow, PyTorch).
• Proven experience with data curation, analysis, and cleaning.
• Track record of publications in top AI/ML conferences and journals.
• Excellent written and verbal communication skills.
• Strong analytical and problem-solving abilities.
• Experience in user research, including conducting interviews and surveys.
• Familiarity with fairness, robustness, and interpretability in AI.
• Knowledge of industry trends and challenges in deploying safe AI systems.
• Ability to collaborate across interdisciplinary teams and with external stakeholders.

Job Description: We are seeking a highly motivated and talented Research Fellow to join our interdisciplinary research team. The successful candidate will conduct cutting-edge theoretical and computational research in the following areas:

Research Areas:

1. Electromagnetism and Plasmonics: Theory and computational modeling of electromagnetism in complex media, plasmonic systems, and metamaterials, with a particular focus on cavity quantum electrodynamics (QED) and interactions between light and matter at the nanoscale.
2. Inverse Design in Nanophotonics and Quantum Nanophotonics: Application of inverse design techniques to optimize and design novel photonic structures and devices, including metasurfaces, photonic crystals, and quantum nanophotonic systems.
3. Plasma and Magnetohydrodynamics (MHD) Modeling: Development and application of advanced plasma modeling tools, such as particle-in-cell (PIC) simulations and magnetohydrodynamics (MHD), to study their interaction with plasmonic or excitonic systems.
4. Novel Optoelectronic Effects: Investigation of new optoelectronic phenomena in low-dimensional materials (e.g., 2D materials, nanowires, and quantum dots) and time crystals, focusing on their potential applications in next-generation devices.
5. Non-Hermitian and Topological Photonics: Study of non-Hermitian systems and topological photonics, including the exploration of novel phenomena such as exceptional points, edge states, and robust modes in photonic systems.

Key Responsibilities:

• Develop and implement theoretical models to describe complex physical systems in the research areas mentioned above.
• Conduct large-scale numerical simulations to study the behavior of plasmonic, nanophotonic, and optoelectronic systems.
• Analyze and interpret simulation results, developing insights into novel physical phenomena.
• Collaborate closely with experimental researchers, providing theoretical guidance and feedback on ongoing experimental work.
• Publish research findings in high-impact, peer-reviewed journals.
• Present research results at internal seminars, conferences, and workshops.
• Contribute to the development of computational tools and code libraries for the group's research.

Qualifications and Skills:

• Required:
  • A Ph.D. in Physics, Applied Physics, Engineering, Applied Mathematics, or a closely related field.
  • Strong background in electromagnetism, quantum mechanics, solid-state physics, and material sciences.
  • Solid experience in computational physics, with proficiency in numerical simulation techniques such as finite-difference-time-domain (FDTD), finite-element method (FEM), particle-in-cell (PIC) simulations, and magnetohydrodynamics (MHD).
  • Ability to develop and modify simulation codes to model complex, multi-physics systems.
  • Strong analytical and problem-solving skills, with the ability to derive and solve equations analytically or numerically.
  • Excellent written and verbal communication skills, with a demonstrated ability to write high-quality research papers and present complex ideas clearly.

Preferred:

• A strong publication record in top-tier journals in related fields.
• Experience with advanced simulation software (e.g., COMSOL, Lumerical, CST, or similar platforms).
• Familiarity with machine learning or artificial intelligence techniques for inverse design and optimization in nanophotonics is a plus.
• Ability to work independently and as part of an interdisciplinary team.
• Demonstrated creativity and innovation in solving complex theoretical and computational problems.
• Experience in collaborative research with experimentalists or other research groups is highly desirable.

Eligibility:

• Ph.D. holders with a relevant background in theoretical/computational physics, engineering, or applied mathematics are encouraged to apply.

Responsibilities:

• Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design.
• Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance.
• Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels.
• Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out.
• Collaborate with design engineers to troubleshoot and resolve simulation issues.
• Provide support to test engineers during post-silicon validation.
• Mentor and guide team members and junior engineers, aiming to enhance verification efficiency.​

Requirements:

• Master in Electrical Engineering or equivalent with 8 years of relevant working experience/ PhD in Electrical Engineering or equivalent with 3 years working experience.
• Extensive understanding of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware-software co-verification methodology.
• Skilled in Verilog, SystemVerilog, Python, Perl, TCL, Shell scripting, C/C++, SystemC, and assembly coding for industry-standard ISAs.
• Familiar with MIPI, AMBA (APB/AHB/AXI) bus protocols, RISC-V/ARM, or DSP cores.
• Experience in verifying designs at RTL and post-P&R gate levels.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Responsibilities:

• Collaborate with Senior Engineers for design requirements and specifications.
• Assist in Analog, mixed-signal, and digital IC design.
• Participate in RTL coding and verification for digital ICs.
• Support design verification tasks.
• Conduct circuit simulations and analysis using Cadence, Synopsys, and Mentor Graphics tools.
• Assist layout engineers with floor planning.
• Analyze and debug silicon failures, suggesting design improvements.
• Contribute to the development of design methodologies to enhance efficiency.
• Document design work and test plans.
• Collaborate with cross-functional teams to ensure successful tape-out.

Requirements:

• Bachelor’s Degree in Electrical Engineering or equivalents.
• At least 2 years of relevant working experience.
• Understanding the IC development flow in advanced CMOS processes, including design, layout, and tape-out.
• Understanding the fundamental theories of digital or analog circuit design.
• Capability to generate inventive designs and circuit solutions tailored to fulfill customer needs.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

· Service clients’ accounts and achieve sales targets

· Manage client’s expectations on project expectations

· Develop project execution strategy

· Obtain quotes from suppliers for materials/fittings for calculation of cost

· Prepare quotation and submission of tender/quotation

· Prepare project budgets and manage cost control based on clients’ budget

· Oversee kick-off meeting with clients

· Submit schedules, concept designs and sample materials for clients to review

· Update organiser/client on the commencement of work

· Coordinate with suppliers to ensure work is completed according to planned schedule

· Oversee handover of project and coordinate with clients regarding defects rectification

· Arrange for invoice billing to clients

· Ensure good client relationship and as primary point of contact for Clients' Project Management team

· Manage specialist design support services and take part in conversion process

· Perform any other adhoc duties

Singapore University of Technology and Design immediately invites applications for multiple Research Assistant positions to work in Singapore, in the following areas:

• Robust perception, planning, and control for field robots
• Simultaneous localization and mapping
• Experimental robotics
• Novel mechanism synthesis and analysis
• Electromechanical system design experience is strongly preferred

Your primary responsibilities include:

• Designing and developing reconfigurable robotic platforms to achieve project goals and KPIs (spanning surveillance, maintenance, and payload-carrying robot platforms)
• Implementing and researching specifications for various subsystem components, component analysis, designing for durability, maintainability, and estimating physical constraints required to achieve expected functionality and reconfigurability .
• Have a good understanding of the electrical system of the robot so as to optimize the mechanical designs
• Have a strong understanding of the PCB design and fabrication
• Have a strong understanding of different manufacturing processes and manufacturing constraints
• Designing mounts for onboard sensors and computing equipment with consideration for dust and waterproof requirements
• Simulating using CAD Solidworks for FEA analysis and Keyshot demonstration
• Experience with electrical and electronic components and the use of fabrication and soldering set is strongly preferred
• Able to effectively communicate ideas and take constructive criticism
• Able to effectively work in a multi-disciplinary team and with third-party vendors

The position requires min Diploma in Engineering Product Development/Information System/ Mechanical/Electrical and Electronics/Computer Engineering or a related area.

Candidates are expected to possess experience in field robotic systems as evidenced by developmental project experiences/publications. Strong commitment to research and development is essential.

RESPONSIBILITY

• Assume a technical expertise in assessing sites, conducting detailed drawings, and estimating Solar project capacity and costs.
• Formulate comprehensive design specifications and functional requirements for the region, ensuring alignment with project needs.
• Complete system designs for projects including site plans, mechanical racking and attachment plans, single-line electrical drawings, specification of balance of system location and interconnection details.
• Conduct in-depth analysis of factors influencing system performance.
• Partner with the O&M Team to evaluate system performance, identify optimization opportunities, and drive continuous improvement initiatives.
• Perform software simulations of solar photovoltaic (PV) system performance & energy production
• Execute design calculations, encompassing voltage drop analysis, fault current assessments, and system optimization strategies.
• Ensure compliance with EPC contract specifications and regulatory requirements, mitigating risks and optimizing project outcomes including on-site engineering support.
• Collaborate closely with contractors to review and approve engineering drawing submissions, maintaining rigorous quality control standards.

QUALIFICATIONS & EXPERIENCE

• Degree/Diploma in Electrical Engineering discipline
• 3 to 5 years’ experience in Solar PV system design / engineering.

SKILLS/COMPETENCIES & PREFERRED CHARACTERISTICS

• Proactive self-starter with an ability to thrive in dynamic environments
• Solution-oriented approach with a track record of overcoming complex challenges and driving innovation
• Collaborative team player and able to guide the drafting team.
• Adaptability and willingness to embrace new technologies and methodologies
• Proficient in Microsoft Office and Excel capabilities for data analysis and reporting
• Proficient in design software such as PV AutoCAD,

Roles and responsibilities:

· To do conceptual and detailed machine design with regard to mechanical aspects;

· To prepare solid models, layouts, views and bills of materials for assigned design machine assemblies and sub-assemblies;

· To prepare final design configurations, layouts, solid models and production/engineering data;

· To assist in preparation of machine documentation, specifications, manual.

Job Requirements:

· Diploma or relevant in Mechanical Engineering;

· Will consider fresh-graduate.

· Preferably with working experience in designing automation systems , jig and fixture ,robotics and conveyor system.

· Proficiency with Solid Works is desirable;

· Ability to lead, manage project and communicate well with customers, vendors, engineers, technicians and team members.

Responsibilities:

• Lead RTL design, simulation, and verification for TetraMem ASIC/SoC products, ensuring robustness.
• Integrate and validate IP blocks for seamless system functionality.
• Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs.
• Collaborate with backend team in RTL coding, implementation, and synthesis for successful tapeout.
• Create and maintain reusable IPs for AI/in-memory computing.
• Support Post-Si testing to ensure product functionality and quality.
• Mentor junior engineers to facilitate their professional growth.
• Contribute to design reviews for improved product performance and reliability.
• Stay current on RTL design methodologies for efficiency and quality.
• Collaborate with cross-functional teams for successful product development.

Requirements:

• Minimum Master in Electrical Engineering with 5 years of working experience with emphasis on RTL/SoC/digital design.
• Proficient in Verilog and SystemVerilog.
• Proficient in VCS, Verdi, or similar industry-standard tools.
• Skilled in pre-layout and post-layout simulation.
• Knowledgeable about the design flow and collaboration with backend teams.
• Familiar with AMBA APB and AXI protocols.
• Familiar with RISC/Arm or other core architectures.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Job description and scopes:

1. Oversee and supervise C&S design, including authoring submissions and coordinating with consultants and architects and architects
2. Design Coordination with Consultant, Client , AC, Inter-Disciplines (MEICA & BS) and Sub Contractors
3. Design Package preparation for MEICA Equipment Plinth and Bolts design
4. Prepare & update Schedules for Architectural Authority Submission & ST Submissions
5. Prepare & update Schedules for Submissions of Deliverables list
6. Prepare RFI & RFC for CSA related items
7. Prepare the workflow of QPD / QPS Roles
8. Prepare the BCA Permit forms for site commencement
9. Review and comments of Architectural authority Submission drawings (such as URA, FSSD, PUB, LTA, NEA ,etc…)
10. Review and comments of BCA Submission of Civil, Structural and Geotechnical work (ST Submissions)
11. Review and comments of IFC drawings , which are extracted from 3D Model
12. Review and comments of Shop drawings, developed by Sub-contractors for Construction
13. Review and comments of Design Drawings and Calculations of Miscellaneous design
14. Review and comments of QA / QC documents
15. BIM 3D Model review and Comments and clash resolutions
16. Follow up on Prolog Submissions
17. Follow up with Inter-disciplines leads for Design Input information for C&S design
18. Change Register for design change control
19. Preparing RFQ Packages for CSA items ( Design Drawings & Specifications ) to Procurement
20. Monitor Site construction Progress & addressing site issues
21. Assist and attending BIM Model Walk-through, Hazop , Almop and Dfs, PSR and Risk management Work shops
22. Co-ordinate and Attending Monthly Progress Meeting & CSA progress meeting with Client & Consultant , and Main QP
23. Co-ordinate and attending SOCT Meeting with potential sub-contractors & suppliers
24. Prepare MOM of CSA Meeting, presentation slides for Monthly progress meeting & preparing Monthly progress report for CSA updates
25. Verifying Claims from design consultant
26. Prefer to assis on the Role of Lifting Engineer , review Lifting plans and approval of Lifting Permit

Requirements (Qualification & Experience):

• With relevant experience in managing similar complexity and scale
• Applicants with Lifting Engineer certification will be preferred

JOB DESCRIPTION

In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition

• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.

• Develop ASIC verification environment including all the respective components such as stimulus, checkers, assertions, monitors and scoreboards.

• Develop directed and constrain-random verification functional tests and simulate using EDA tools to verify functional spec is working

• Execute verification plans, including design bring-up, DV bring-up, regression enabling for all the features.

• Collaborate with digital design team to debug functional testcases and deliver functionally correct designs

The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment

JOB REQUIREMENTS

· BSEE or MSEE, entry level

· Strong communication, analytical and documentation skills and ability to interface with other groups

· Strong VLSI functional verification experience, preferably with exposure to complex, high speed custom VLSI products

· Strong hardware functional verification language and Object-oriental language development skill. Prefer with SystemVerilog/ UVM experience

· Familiar with ASIC verification methodology, tools, and development flow

· Working experience or familiar with Ethernet L2/L3 switch/router, SOC, AMBA bus, high-speed IO (USB-2/3, PCIe gen2/3, SATA), Flash controller, or CPU peripherals

A research position is available at the Singapore University of Technology and Design (SUTD). The research focuses on semantic communications, resource allocation, and edge AI.

Candidates with strong publication records in relevant areas are encouraged to apply. The candidate should have:

• Bachelor’s / Master's degree in computer science or related degree
• Strong publication record in top-tier IEEE conferences/journals
• Proficient in oral and written English

Kindly note that only shortlisted candidates will be notified.

JOB DESCRIPTION

· Work on SoC architecture discussion and optimization with architect; SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;

· Work on SoC floorplan with architect and APR; SoC power check; SoC timing constraints and review support; SoC DFT support; SoC verification plan and SoC verification support

JOB REQUIREMENTS

· Bachelor’s or Master’s Degree in Electronic Engineering with ASIC design experience.

· Experience with ASIC design flow

· Experience in RTL coding, RTL and gate-level simulation, logic synthesis, static timing analysis, timing closure and verification

· Good understanding of DFT

· Familiar with UNIX/ Linux environment and scripting

· Good communication and interpersonal skills

· Strong analytical and problem-solving skills

JOB DESCRIPTION

In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition

• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.

• Develop ASIC verification environment including all the respective components such as stimulus, checkers, assertions, monitors and scoreboards.

• Develop directed and constrain-random verification functional tests and simulate using EDA tools to verify functional spec is working

• Execute verification plans, including design bring-up, DV bring-up, regression enabling for all the features.

• Collaborate with digital design team to debug functional testcases and deliver functionally correct designs

The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment

JOB REQUIREMENTS

· BSEE or MSEE, entry level

· Strong communication, analytical and documentation skills and ability to interface with other groups

· Strong VLSI functional verification experience, preferably with exposure to complex, high speed custom VLSI products

· Strong hardware functional verification language and Object-oriental language development skill. Prefer with SystemVerilog/ UVM experience

· Familiar with ASIC verification methodology, tools, and development flow

· Working experience or familiar with Ethernet L2/L3 switch/router, SOC, AMBA bus, high-speed IO (USB-2/3, PCIe gen2/3, SATA), Flash controller, or CPU peripherals

Project Overview

This research project aims to grasp dynamic changes in hotel capital investments and their influences on tourism-related local businesses before, during, and after the pandemic on two geographic scales -- region (Asia-Pacific) and city (Singapore). This aim is outlined by the following three objectives:

• Examining the significance of sustainable development attributes in explaining the spatial distribution of new hotel development projects across selected cities in the Asia-Pacific region;
• Estimating the influences of new hotel development projects on the establishment of tourism-small business enterprises within and around hotel districts in Singapore; and
• Drawing evidence-based policy implications along with specific measures for cities to rebuild and expand the capacity of urban tourism in the Asia-Pacific region and Singapore.

Job Description

The Research Assistant (one-year contract) will undertake the following research activities:

• Meeting with the principal investigator (PI) and team members regularly;
• Supporting the progress of key tasks;
• Collecting and organizing international hotel investment and other urban spatial datasets
• Visualizing multiple urban tourism, transport, environment, and economic attributes on a geographic information system (GIS) platform; &
• Developing hotel location choice and small business birth models
• Exploring new software applications for spatial data analyses.

This Research Assistant position will be arranged based on the Urban Planning & Economic/Environmental Policy Research Team, led by PI Prof. Jin Murakami, with support from the Humanities, Arts and Social Sciences (HASS) Cluster/Green Economy and Sustainability Initiative in SUTD.

Requirements

• Bachelor degree in Urban Planning, Environmental Studies, Economics, Business, Civil Engineering, Systems Engineering, Information Science, or related fields*
• Strong data management and quantitative analysis skills
• Proficiency with programing, coding, and/or statistical software (e.g., Python, R, STATA)
• Knowledge and experience of GIS software applications (ArcGIS and/or QGIS)
• Interest in data visualization skills – preferred
• Sufficient report writing and communication skills in English

To Apply

Interested applicants should email:

(1) a cover letter expressing specific interest in this position.

(2) a detailed CV with information on (i) education qualifications, (ii) working

experience, (iii) list of publications, (iv) name/title/contact of at least one reference, and (v) citizenship status.

(3) any writing sample to Dr. Jin Murakami at [email protected]. Subject should indicate: Full-time Research Assistant – Urban Tourism Research

We regret that only shortlisted candidates will be notified.

Responsibilities:

• Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design.
• Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance.
• Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels.
• Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out.
• Collaborate with design engineers to troubleshoot and resolve simulation issues.
• Provide support to test engineers during post-silicon validation.
• Mentor and guide team members and junior engineers, aiming to enhance verification efficiency.​

Requirements:

• Master in Electrical Engineering or equivalent with 8 years of relevant working experience/ PhD in Electrical Engineering or equivalent with 3 years working experience.
• Extensive understanding of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware-software co-verification methodology.
• Skilled in Verilog, SystemVerilog, Python, Perl, TCL, Shell scripting, C/C++, SystemC, and assembly coding for industry-standard ISAs.
• Familiar with MIPI, AMBA (APB/AHB/AXI) bus protocols, RISC-V/ARM, or DSP cores.
• Experience in verifying designs at RTL and post-P&R gate levels.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Responsibilities:

• Collaborate with Senior Engineers for design requirements and specifications.
• Assist in Analog, mixed-signal, and digital IC design.
• Participate in RTL coding and verification for digital ICs.
• Support design verification tasks.
• Conduct circuit simulations and analysis using Cadence, Synopsys, and Mentor Graphics tools.
• Assist layout engineers with floor planning.
• Analyze and debug silicon failures, suggesting design improvements.
• Contribute to the development of design methodologies to enhance efficiency.
• Document design work and test plans.
• Collaborate with cross-functional teams to ensure successful tape-out.

Requirements:

• Bachelor’s Degree in Electrical Engineering or equivalents.
• At least 2 years of relevant working experience.
• Understanding the IC development flow in advanced CMOS processes, including design, layout, and tape-out.
• Understanding the fundamental theories of digital or analog circuit design.
• Capability to generate inventive designs and circuit solutions tailored to fulfill customer needs.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [email protected] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628