Singapore University of Technology and Design (SUTD) is actively seeking applications for Senior Research Assistant/ Research Fellow positions at the intersection of optimization and quantum information, funded through the QEP 2.0 program. This role offers a unique opportunity to apply mathematical optimization techniques to address pivotal challenges in the realm of quantum information theory.

Qualifications:

- Educational Background: A Masters or Ph.D. in Applied Mathematics or Computer Science.

- Optimization Expertise: Proven experience in the application of optimization techniques to tackle complex computational problems.

- Publication Track Record: A strong history of influential publications in high-impact journals or conferences within the pertinent fields.

Principal Investigator:

The successful candidate will collaborate with Assistant Professor Antonios Varvitsiotis, affiliated with the Engineering Systems and Design Pillar (https://sites.google.com/site/antoniosvarvitsiotis/)

Join Artistori as we seek enthusiastic and dedicated educators specializing in fine art and visual arts. If you're passionate about nurturing creativity in children and enjoy guiding them through various artistic expressions, we invite you to be part of our team. Embrace the transformative power of arts education in fostering individual growth, from essential life skills to academic success. If you share our commitment to shaping young minds through art, we welcome you aboard!

We're seeking experienced art educators who:

1. Are proficient in and adaptable to inquiry-based pedagogy approaches.
2. Excel in generating curriculum ideas and crafting effective curriculums.
3. Have experience teaching a diverse range of ages, from 2 years old to adults.
4. Value parent involvement and believe in keeping parents informed about their child's activities, objectives, and performance.
5. Emphasize engagement and interest as catalysts for children's development and learning.
6. Foster a fun, engaging, and enthusiastic class atmosphere to promote learning.
7. Embrace multiple roles to effectively communicate, learn, discover, and collaborate with students.
8. Recognize the power of the arts in conveying children's interests, expressions, imaginations, and ideas, and can teach children to articulate them through artistic language.

Requisites:

• Strong communication and presentation skills.
• Excellent classroom, time, and student management abilities.
• Demonstrated initiative and a positive attitude towards nurturing teaching and learning.
• Proficiency in artistic knowledge and fine art techniques.

Qualifications

• Professional qualification in art, art education, visual arts, or fine arts.
• Early childhood certification is advantageous.
• Experience and skill in pottery and ceramics are valued.
• Proficiency in digital platforms is a plus.

Drop an email to us with your CV / Resume: [email protected]

Whatsapp: 88765551

WeChat: Artistori

Website: http://www.artistori.com

Facebook: http://www.facebook.com/artistori

Instagram: https://www.instagram.com/artistori_school

小红书: Artistori

意言社 Artistori

用艺术表达语言，让语言丰富艺术

Your Story, Your Art

We are looking for a self-motivated candidate with expertise in high performance digital design and system level architecture modeling to join our Heterogeneous System design team. This candidate will work closely with IME’s advanced packing team and contribute to the exploration, optimization and development of multicore & multi-chip system using IME’s heterogeneous integration platform.

Job Description:

· Digital IC Design and system-level exploration:

o Lead and contribute to the design and development of digital integrated circuits, ensuring they meet performance and functionality requirements.

o <!-Emphasize a system-level perspective in the design process, considering overall system architecture and functionality.

o Apply a deep understanding of cryogenic temperature effects on digital ICs and implement design strategies for optimal performance in low-temperature environments.

o Incorporate Edge AI principles into digital IC designs, enabling efficient and intelligent processing at the edge of the network.

o RTL implementation for custom circuit design using Verilog/SystemVerilog

o Derive specs and implement necessary customized and highly efficient building blocks such as systolic array, data path controller, scheduler, integer and floating-point processing engine, FFT, etc which are frequency used in various computing architecture such as in-memory computing, deep learning and neuromorphic computing.

· Simulation, Verification, and Implementation:

o Conduct thorough simulation and verification of digital designs to validate functionality and performance.

o Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration

o Perform timing analysis and collaborate with the team to optimize designs for timing closure.

o Contribute to power analysis activities and implement power-efficient design techniques.

Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II.

· Collaborate closely with cross-functional teams, including hardware and software engineers, to seamlessly integrate digital ICs into the overall system architecture.

· Prepare detailed design documentation, including specifications, test plans, and reports.

· Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues.

· Bring creative and innovative solutions to design challenges, staying abreast of industry trends and emerging technologies.

Requirements: Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

We are looking for a self-motivated candidate with expertise in high performance digital design and system level architecture modeling to join our Heterogeneous System design team. This candidate will work closely with IME’s advanced packing team and contribute to the exploration, optimization and development of multicore & multi-chip system using IME’s heterogeneous integration platform.

Job Description:

· Digital IC Design and system-level exploration:

o Lead and contribute to the design and development of digital integrated circuits, ensuring they meet performance and functionality requirements.

o <!-Emphasize a system-level perspective in the design process, considering overall system architecture and functionality.

o Apply a deep understanding of cryogenic temperature effects on digital ICs and implement design strategies for optimal performance in low-temperature environments.

o Incorporate Edge AI principles into digital IC designs, enabling efficient and intelligent processing at the edge of the network.

o RTL implementation for custom circuit design using Verilog/SystemVerilog

o Derive specs and implement necessary customized and highly efficient building blocks such as systolic array, data path controller, scheduler, integer and floating-point processing engine, FFT, etc which are frequency used in various computing architecture such as in-memory computing, deep learning and neuromorphic computing.

· Simulation, Verification, and Implementation:

o Conduct thorough simulation and verification of digital designs to validate functionality and performance.

o Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration

o Perform timing analysis and collaborate with the team to optimize designs for timing closure.

o Contribute to power analysis activities and implement power-efficient design techniques.

Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II.

· Collaborate closely with cross-functional teams, including hardware and software engineers, to seamlessly integrate digital ICs into the overall system architecture.

· Prepare detailed design documentation, including specifications, test plans, and reports.

· Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues.

· Bring creative and innovative solutions to design challenges, staying abreast of industry trends and emerging technologies.

Requirements: Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

We are looking for a candidate for high-speed analog integrated circuit design. This candidate will contribute to the development of high linearity silicon photonics modulators for 6G and beyond communication systems. This requires the candidate to work closely with the optics team on the electro/optical co-design as well as system integration and validation.

• Perform system level analysis and design, to derive circuit-level design specifications
• Design and tapeout ICs which include state-of-the-art circuit blocks, e.g. wideband linear low-noise amplifier and transimpedance amplifier with a focus on circuits interfacing with silicon photonics elements
• Work together with team to investigate novel circuit/system solutions to create new inventions

Job Requirements

• Qualification & Field of Study: Minimum Bachelor’s degree and above in Electronic Engineering
• Min. Years of Experience: Minimum 2-years of transistor level analog circuit design experience

Other Requirements (e.g. Skills, Competencies)

• Good understanding of CMOS analog IC design methodologies and successful tapeout experience
• Familiar with analog IC design and verification flow
• Industry experience would be a plus
• Familiar with the IC test equipment such as oscilloscope, spectrum analyzer, etc.
• Good communication skills (both written and spoken)
• Able to generate high quality scientific publications and patents
• Team player, quick learner and self-driven

Responsibilities:

• Conduct Solution Architecture activities when required on Bids and Projects, in close collaboration with Systems Engineers and reporting to the PDA in that case. In charge of proposing Solution Compliance.
• Support the Solution Orientation Review (SOR) for Bids in collaboration with the Solution Engineering Manager (Bids), Services Engineering and assigned bid team members.
• Propose draft DVa and report to the PDA in terms of Solution definition for allocated Bids/Projects.
• Ensure that the design of the Solution satisfies:
  • Customer needs and contractual requirements for a project,
  • Contractually applicable technical standards,
  • Alignment with the Product Policy,
  • Cost effectiveness, and
  • Applicable design legislation, rules and regulations.
• Ensures, with the support of Specialty Engineering experts & HSE stakeholders that:
  • Solution design takes into account contract requirements in terms of Safety, Security and Human Factors and applicable legislation, rules & regulations, including Environmental/HSE requirements & standards,
  • Related certification activities are performed correctly.
• Particular focus on risks qualification and quantification and mitigation actions at Bid phase and follow-up at Project phase. Risks must be understood and mastered.
• Participate in specific actions plans and dedicated task forces as allocated to solve complex technical problems.
• Contribute to elaborate the TopSKY-ATC product policy through commonalising specific Solutions required by projects and support the HE Product Design Authority in maintaining a rigorous Product policy.
• Take charge of a Technical Speciality when required (e.g. Network & Infrastructure) with the aim to:
  • be the subject-matter expert within the organization,
  • provides a conduit for the sharing of state-of-the-art knowledge across the discipline,
  • be responsible for capitalisation within his/her discipline.
• Pro-actively share knowledge with the experts network inside the AMS Business Line and participate when required into external events in the technical & ATM expert fields to represent Thales AMS.

Requirement:

• Tertiary Qualifications in Engineering
• Degree in computer sciences (minimum Bachelor of Sciences) and network discipline
• 7 years minimum of experience holding positions in systems engineering and/or software engineering and/or integration on complex software-centric real-time systems.
• A proven track-record in supporting the design of Solutions for complex System Of Systems.
• Proven capability to work in a multi-cultural environment and with variety of international customers.
• Experience in the ATM Domain is mandatory.
• Language: fluent English, French would be a plus.
• International work context
• Aptitude to work effectively as part of a team.
• Resilience under pressure.
• Capacity to learn quickly.
• Capability to manage various stakeholders having different objectives.

We are looking for a candidate for high-speed analog integrated circuit design. This candidate will contribute to the development of high linearity silicon photonics modulators for 6G and beyond communication systems. This requires the candidate to work closely with the optics team on the electro/optical co-design as well as system integration and validation.

• Perform system level analysis and design, to derive circuit-level design specifications
• Design and tapeout ICs which include state-of-the-art circuit blocks, e.g. wideband linear low-noise amplifier and transimpedance amplifier with a focus on circuits interfacing with silicon photonics elements
• Work together with team to investigate novel circuit/system solutions to create new inventions

Job Requirements

• Qualification & Field of Study: Minimum Bachelor’s degree and above in Electronic Engineering
• Min. Years of Experience: Minimum 2-years of transistor level analog circuit design experience

Other Requirements (e.g. Skills, Competencies)

• Good understanding of CMOS analog IC design methodologies and successful tapeout experience
• Familiar with analog IC design and verification flow
• Industry experience would be a plus
• Familiar with the IC test equipment such as oscilloscope, spectrum analyzer, etc.
• Good communication skills (both written and spoken)
• Able to generate high quality scientific publications and patents
• Team player, quick learner and self-driven

We are looking for a self-motivated candidate with expertise in high performance digital design, DSP and mixed signal modeling join our cryogenic CMOS-based quantum control project. This candidate will work closely with our digital and analog design team as well as with the local physics and material designers to develop low-power, high fidelity and highly scalable control and read-out SoC for superconducting qubit-based quantum computing applications.

Job Description:

· Digital IC Design and system-level exploration:

o Lead and contribute to co-optimization between on-chip memory and DSP design and analog front-end (i.e. DAC, BPF, Mixer, LNA and ADC) to ensure high quantum control/readout as well as to optimize power consumption per channel

o Emphasize system-level perspective in the design process, considering overall system architecture and functionality

o Apply a deep understanding of cryogenic temperature effects on digital ICs and implement design strategies for optimal performance in low-temperature environments

o RTL implementation for custom circuit design using Verilog/SystemVerilog with focus on DDS, Filter and Error Correction Code

· Simulation, Verification, and Implementation:

o Conduct thorough simulation and verification of mixed signal designs to validate quantum control fidelity and digital-analog interface throughput

o Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration

o Perform timing analysis and collaborate with the team to optimize designs for timing closure

• Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II
• Collaborate closely with cross-functional teams, including hardware and software engineers, to seamlessly integrate digital ICs into the overall system architecture
• Prepare detailed design documentation, including specifications, test plans, and reports
• Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues
• Bring creative and innovative solutions to design challenges. Stay abreast of industry trends and emerging technologies
• Test and verify fabricated chip using FPGA and other lab equipment such as logic analyzer and oscilloscope

Requirements: Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

• Need experience in Architectural metal works, metal cladding, Ceiling panels, Glass Wall, Glass Railing, Sky lights, Stainless Steel & Aluminium works.
• Planning of shop drawings submission schedule to control the sequence and time frame for development of shop drawings.
• Prepare documents/samples submission schedule to control the sequence and timing for samples submission/approval with preferable float time allowed for procurements.
• Co-ordinate all related design matters with Consultants/ Client.
• Ensure main contract and sub-contract designs co-ordinated fulfil all design requirements.
• Co-ordinate with Contract team for any formal and informal changes made by Consultants.
• Co-ordinate with Contract team for proper sequence of sub-contract awards.
• Resolve technical problems for team.

Interested applicants, please apply online or send your resume in WORD format to [email protected] & [email protected]

Thank you for your application but we regret that only shortlisted candidates will be notified.Design / Technical Manager

We are looking for a candidate for high-speed analog and mixed-signal integrated circuit design. This candidate will contribute to the development of high-speed silicon photonics transceiver for next generation wireline communication system. This requires the candidate to work closely with the optics team on the electro/optical co-design as well as system integration and validation.

• Perform system level analysis and design, to derive circuit-level design specifications.
• Design and tapeout ICs which include state-of-the-art circuit blocks e.g. analog-to-digital converter, equalizers (CTLE, DFE) as part of the high-speed data link system.
• Work together with team to investigate novel circuit/system solutions to create new inventions

Job Requirements

• Qualification & Field of Study: Minimum Bachelor’s degree and above in Electrical Engineering
• Min. Years of Experience: Minimum 2-years of transistor level analog circuit design experience

Other Requirements (e.g. Skills, Competencies)

• Good understanding of CMOS analog and mixed-signal IC design methodologies and successful tapeout experience
• Familiar with analog and mixed-signal IC design and verification flow
• Industry experience would be a plus
• Familiar with the IC test equipment such as oscilloscope, spectrum analyzer, etc.
• Good communication skills (both written and spoken)
• Able to generate high quality scientific publications and patents
• Team player, quick learner and self-driven

We are looking for a self-motivated candidate with expertise in high performance digital design, DSP and mixed signal modeling join our cryogenic CMOS-based quantum control project. This candidate will work closely with our digital and analog design team as well as with the local physics and material designers to develop low-power, high fidelity and highly scalable control and read-out SoC for superconducting qubit-based quantum computing applications.

Job Description:

· Digital IC Design and system-level exploration:

o Lead and contribute to co-optimization between on-chip memory and DSP design and analog front-end (i.e. DAC, BPF, Mixer, LNA and ADC) to ensure high quantum control/readout as well as to optimize power consumption per channel

o Emphasize system-level perspective in the design process, considering overall system architecture and functionality

o Apply a deep understanding of cryogenic temperature effects on digital ICs and implement design strategies for optimal performance in low-temperature environments

o RTL implementation for custom circuit design using Verilog/SystemVerilog with focus on DDS, Filter and Error Correction Code

· Simulation, Verification, and Implementation:

o Conduct thorough simulation and verification of mixed signal designs to validate quantum control fidelity and digital-analog interface throughput

o Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration

o Perform timing analysis and collaborate with the team to optimize designs for timing closure

• Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II
• Collaborate closely with cross-functional teams, including hardware and software engineers, to seamlessly integrate digital ICs into the overall system architecture
• Prepare detailed design documentation, including specifications, test plans, and reports
• Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues
• Bring creative and innovative solutions to design challenges. Stay abreast of industry trends and emerging technologies
• Test and verify fabricated chip using FPGA and other lab equipment such as logic analyzer and oscilloscope

Requirements: Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

We are looking for a candidate for high-speed analog and mixed-signal integrated circuit design. This candidate will contribute to the development of high-speed silicon photonics transceiver for next generation wireline communication system. This requires the candidate to work closely with the optics team on the electro/optical co-design as well as system integration and validation.

• Perform system level analysis and design, to derive circuit-level design specifications.
• Design and tapeout ICs which include state-of-the-art circuit blocks e.g. analog-to-digital converter, equalizers (CTLE, DFE) as part of the high-speed data link system.
• Work together with team to investigate novel circuit/system solutions to create new inventions

Job Requirements

• Qualification & Field of Study: Minimum Bachelor’s degree and above in Electrical Engineering
• Min. Years of Experience: Minimum 2-years of transistor level analog circuit design experience

Other Requirements (e.g. Skills, Competencies)

• Good understanding of CMOS analog and mixed-signal IC design methodologies and successful tapeout experience
• Familiar with analog and mixed-signal IC design and verification flow
• Industry experience would be a plus
• Familiar with the IC test equipment such as oscilloscope, spectrum analyzer, etc.
• Good communication skills (both written and spoken)
• Able to generate high quality scientific publications and patents
• Team player, quick learner and self-driven

Tanglin Mission

Tanglin Trust School Singapore has a long tradition of providing British-based learning with an international perspective. At Tanglin we strive to make every individual feel valued, happy and successful. Responsibility, enthusiasm and participation are actively encouraged and integrity is prized. Working together in a safe, caring yet stimulating environment, we set high expectations whilst offering strong support, resulting in a community of lifelong learners who can contribute with confidence to our world.

Our Vision

We aspire to be the best school in the world with a dynamic learning community which nurtures and inspires every individual to be the best they can be. Our core values of Respect, Responsibility and Purpose are at the heart of everything we do across the school.

The Role

This is a rare and exciting opportunity to join a DT department within a well-established, outstanding school. Our vision is that the department will be modern and forward-thinking, with learning located in authentic contexts, and that the curriculum will reflect the successful candidate’s creative energy. He/she will have outstanding subject knowledge, a passion for designing and will be at the cutting edge of technological innovation within the field. The successful candidate will be a teacher with commitment, integrity and excellent communication skills and a teacher with flexibility, resilience and a caring approach towards students.

Key Responsibilities

1. Learning & Teaching

• Manage an effective, enthusiastic, and safe learning environment.
• Deliver the curriculum to assigned classes in accordance with the timetable.
• Differentiate lessons according to the abilities and learning needs of individual students.
• Promote independent learning by adopting teaching and learning strategies that develop the competence and confidence of every student.
• Seek to develop students’ attributes through the Tanglin Learner Profile, as well as seek opportunities to develop their own attributes through that framework.
• Ensure the thorough implementation of subject specifications, teaching schemes, assessment policies and reporting procedures.
• Create opportunities for students to develop confidence in the subject through carefully planned and managed activities.
• Support a departmental and whole school culture of innovation that includes varied and exciting teaching approaches, technological integration, and thoughtful evaluation.
• Possess the flexibility required to teach a range of materials, topics, and ability levels.
• Possess the flexibility required to teach either pathway (A level or IB) in the Sixth form.

2. Planning & Development

• Take responsibility for at least one aspect of D&T curriculum development each year following discussion and negotiation with the department leadership team (eg, creating a new scheme of work, drafting of departmental policy, organisation of trip).
• Assist the D&T department leadership team in evaluating and developing the new curriculum.
• Take advantage of opportunities for professional development offered by Tanglin.
• Take responsibility for their professional development and that of colleagues by occasionally leading departmental inset or department meetings in an area of expertise.
• Assist the HOD (Head of Department) in identifying areas for development in D&T within the broader aims of the school development plan.
• Collaborate with colleagues in the planning and delivery of schemes of work, including the choice of appropriate teaching and learning methods to meet the needs of the subject and of different pupils.
• Assist the HOD in adapting curriculum content and methods of teaching and examining as appropriate.
• Support a school culture of innovation that includes technological integration.
• Be supportive of and open to the frequent change that characterises a school such as Tanglin.

3. Management of Resources and the Teaching Environment:

• Assist the HOD in identifying appropriate resources within the limits of the departmental budget.
• Assist the HOD in ensuring that departmental rooms present stimulating environments that help to influence pupils’ attitudes positively towards D&T.

4. Assessment, Recording & Reporting

• Ensure students’ work is regularly assessed according to D&T departmental policy and that homework is in line with school policy.
• Report to parents in accordance with the school’s reporting policy as laid down in the Staff Handbook.
• To use information gained from assessment, recording and reporting procedures to generate further improvement in pupil achievement.
• Assist the HOD in the setting and marking of school examinations and to supervise entries for external examinations.

5. Pastoral and Co-Curricular

• Lead the development of the F1 in Schools program in D&T.
• Contribute to co-curricular activities that broaden pupils’ experiences and contribute to the general life of the school.
• When required, take on a form tutor role in the Senior School and fulfil the responsibilities of that position.
• Follow the School’s policies and procedures regarding discipline and behaviour, daily routines, duties, homework, leave of absence, and visits, as laid down in the Staff Handbook.
• Be responsible for reporting any concerns about a child to the Designated Safeguarding Lead.

6. Communication and Liaison

• Help to establish an ability to spot and solve problems and to increase resilience in learning, through your own enthusiasm for the subject.
• Contribute wholeheartedly to D&T department activities such as supporting each school with projects, planning ‘House Day’ activities, ‘Children’s University’ and transition days.
• Attend and contribute to meetings of a professional nature with HOD, HOF, HOY, SSLT and in other circumstances when requested.
• Liaise with the HOD and HOF in respect of pupil records, rewards, and sanctions.
• Maintain appropriate links with teaching colleagues in all sections of the school and foster cross-curricular links where appropriate.
• Liaise with members of the Learning Support Team regarding individual students who may have exceptional needs, to ensure that those needs are understood, planned for and met.
• Liaise with pastoral staff, including form tutors, Heads of Year, the Assistant Heads of School and the Head of Careers on matters pertaining to the study of D&T.
• Contribute to the strengthening of the parent-teacher partnership in individual and whole school initiatives as and when required.
• Assist the HOD in developing effective links with the wider community to extend the study of D&T and enhance teaching and learning.

Job Description:

We are looking for a highly motivated computational scientist with a deep understanding of chemistry/cheminformatics and structural biology to develop new AI models for ligand discovery. You will be working on a large collaborative project to build up A*STAR’s computational drug discovery capabilities. The candidate is expected to be familiar with the latest generative models. Familiarity with molecular docking programs is a plus.

Job Requirements:

• PhD degree in life sciences, chemistry, computational biology, or a related discipline
• Passion for science and research
• Highly motivated
• Proficiency in the use of machine learning frameworks (e.g. PyTorch, TensorFlow)
• Experienced in developing generative models
• Strong knowledge of chemistry/cheminformatics and structural biology
• Able to work independently and as part of a team
• Excellent written and oral communication skills

The above eligibility criteria are not exhaustive. A*STAR may include additional selection criteria based on its prevailing recruitment policies. These policies may be amended from time to time without notice. We regret that only shortlisted candidates will be notified.

Requirements :

1) A Degree in Civil or Structural Engineering from a recognized university or its equivalent recognized by the Professional Engineer Board, Singapore. A diploma holder with design experience will also be considered.

2) Minimum 2 years of design experience in Building projects and/or Earth Retaining Structures.

3) Conversant with local codes and authority submission procedures.

4) Competent in common engineering design software, analytical tools and BIM software.

5) Familiar with precast concrete, post-tensioned concrete and steelwork design, knowledge of MET design will be an advantage.

6) Proactive, responsible and keen to work in a team.

7) Excellent interpersonal, good verbal and written communication skills.

Job Description :

1) Perform Civil/Structural engineering design and analysis.

2) Participate in the BIM process. Involvement in the collaboration with peers and fellow Consultants from other disciplines.

3) Coordinate, monitor and track authority submissions for Projects.

4) Conduct feasibility studies, and inspections and prepare technical reports.

5) Attend meetings and design workshops, when necessary.

6) Liaise with Engineers and/or Consultant teams during the implementation of projects.

Responsibilities:

• Design and implement an intrusion detection system (IDS) specifically for monitoring and securing the IT-OT interfaces within power grid environments.
• Capture, decode, and analyze network traffic in the IT-OT domain of the ICS to detect and respond to potential security threats.
• Develop and refine algorithms and methods for detecting anomalous behavior or unauthorized access within the network.
• Collaborate with cybersecurity and network teams to integrate the IDS into the existing security infrastructure and workflows.
• Conduct continuous monitoring and periodic testing of the IDS to ensure its effectiveness and to update its capabilities in response to emerging threats.
• Prepare and maintain documentation related to the IDS, including system design, configuration, and operational procedures.
• Stay updated with the latest cybersecurity trends and advancements in intrusion detection technologies to recommend improvements to the IDS.

Qualifications & Experience:

• Bachelor’s or Master’s degree in Engineering, Computer Science, Information Technology, or related fields.
• Proficient in Python programming with demonstrated experience in developing and maintaining software solutions.
• Solid understanding of computer networks, including network architectures, protocols, and security measures.
• Experience with network analysis tools, with a preference for candidates familiar with Wireshark.
• Knowledge of Industrial Control System (ICS) protocols such as IEC 61850, MODBUS, and Ethernet/IP (ENIP) is highly beneficial.

Skills and Abilities:

• Strong analytical and problem-solving skills with a keen attention to detail.
• Ability to work independently and in a team environment, managing multiple priorities with minimal supervision.
• A proactive approach to identifying risks and implementing preventative measures.

• Manages day-to-day communications including coordinating and work with internal and external personnel
• Maintain and Monitor Project Plans, Schedules
• Supports technical team on document management, including submissions
• Organising, Attending, Participating in Contractors Meetings
• Manage and supervise project works as well as oversee all workers, and liaise with Interior Designer to ensure proper work execution and good workmanship
• Liaise and co-ordinate with Clients, Interior Designer, sub contractors on all project matters
• Resolve any Clients and / or residents’ complaints / feedbacks
• Coordinate the project work to ensure successful completion as well as hand over to the Clients
• Track work progress and submit progress report so as to ensure that the projects are executed on time and within budget

• Position :Design Executive/Drafter (BIM/CAD- CIVIL/STRUCTURAL)
• Location : Near Ubi MRT
• Working hours : 5 days work week, Monday - Friday : 8.30am to 5:30pm,
• Salary (commensurate with experience) : Up to $64200 + Variable bonus+ 14 days Annual leave
• Duration : Permanent
• Industry : Building/Construction

Main Responsibilities

• Prepare and facilitate design drawings using BIM and CAD technologies for building construction.
• Liaise and coordinate with main contractor and other trades for cross-team support on BIM software.
• Ensure all models are compatible and BIM data are made available to all project participants.
• Collaborate within design team and other relevant departments to ensure all drawings are in
• order as per design requirements.
• Any other tasks as may be assigned from time to time.

Requirements

• Certificate/Diploma/Degree in Architectural / Civil Engineering or equivalent
• 1-2 years of related work experience in similar capacity for construction and architecture
• projects
• roficient in MS Office, Revit, Navisworks and AutoCAD software
• Knowledge of DGN, DWF, IFC and MicroStation
• Knowledge of native formats of BIM authoring or BIM related applications for design reviews environment

Email to [email protected]

Do visit Search Personnel Pte Ltd for more job listings.

***We DO NOT charge our candidates any referral fee nor bind them with any contract.***

Joie Chang

Deputy Consulting Director (APAC)

Reg no.: R2090601 | EA No: 13C6684

The Humanities, Arts, and Social Sciences (HASS) Cluster at Singapore University of Technology and Design (SUTD) seeks applicants for a full-time lecturer or senior lecturer teaching-track position in the social sciences. Appointments will be made on an initial two- or three-year contract with the possibility of renewal, including opportunities for career development and promotion within the teaching-track.

We seek applicants from any of the social sciences (economics, sociology, anthropology, psychology, etc.) who have a strong background and interest in teaching classical and contemporary social science theory and methods. Successful applicants will teach in our team-taught introductory core course Social Science: Understanding Culture, Society and Behaviour. In addition, successful applicants will also teach 1 or 2 electives of their own design that contribute to our cluster’s teaching mission as a HASS cluster within an engineering and design university.

Candidates who can contribute through teaching and research to our Minor Degree program in Design, Technology, and Society—a design-focused variant of Science, Technology, and Society studies (STS)—are especially encouraged to apply. Potential to teach in our new Master’s degree in Human-Centred Design is also valued.

Applicants should have a Ph.D. in a social science discipline (broadly construed), with a proven track record of effective teaching and research in the applicant’s field of specialty.

The teaching load for teaching-track faculty is 6.5 course credits per calendar year.

Application Details

SUTD is a new research university established in collaboration with MIT and offers degrees in engineering, computer science, and architecture with a strong emphasis on nurturing socially cognizant innovators, technologists, designers, and entrepreneurs. The HASS department plays a pivotal role in the university’s commitment to world-class teaching and research excellence. The current HASS faculty bring core expertise in anthropology, history, literature, psychology, sociology, urban studies, and the digital humanities.

Candidates should submit the following materials through the SUTD Careers page.

1. A cover letter

2. A curriculum vitae

3. A statement of teaching experience and philosophy

4. A statement of current and future research plans

5. A 500-word description and selected bibliography of up to ten readings for two courses you may wish to offer OR two course syllabi

6. A writing sample, such as a submitted journal article

7. Names, affiliations, and email addresses of two references. Please note that candidates who advance to the interview stage will be asked to submit two letters of recommendation at that point. Please have your recommenders ready to send their letters via Interfolio or another means.

Responsibilities:

• Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips.
• Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff
• Block coordinator role for more than 5~10 blocks, solving the critical issue and give the solution to block owners.
• TOP role for the complicated hierarchical chip (more than 20 Million instances plus 500+ macros), doing floorplan and partition, responsible for full chip tapeout

Requirements:

• Bachelor/Master Degree in Electrical/Computer Engineer.
• Experience in physical design with tape-outs.
• Knowledge of complete Netlist-to-GDS flow, Synopsys/Cadence tools like ICC2 or Innovus.
• Good in script programming with Perl, TCL/TK or other languages.

We are looking for a Chef who has rich experience in preparing North Indian Delicacies.

Job Requirements:

· At least 10 years of working experience as North Indian Chef.

· Knowledge about recipes of various Authentic North Indian dishes.

· Rich experience in preparing Indian Soups, Appetizers, Curries and Indian Chinese.

· Experience as Tandoor Chef is added advantage.

· Experience in preparing Indian sweets & desserts.

· Knowledge and Experience to introduce new dishes as “specials of the week".

· Ability to revisit and revise existing menu to better suit the customer needs.

· To cook tasty food using natural spices & healthy ingredients to bring the authentic flavour to dishes.

· To keep track of the stock of groceries, vegetables and meat and order appropriately.

· To avoid food wastage with proper planning.

· To speak English and Hindi fluently.

· To work with great team spirit with other chefs and service staff.

· To maintain kitchen neat and tidy always as per SFA & NEA regulations.

Wash toilets

Wipe table/chairs

Vacuum/Sweep/Mop

Wipe glass

Wipe cabinets

Sweep open air carpet for leaves

Clean bin centre

Maintain cleanliness of compound

• Position : Sales Design Engineer | BMS/HVAC/ACMV | Up to $5500 + VB
• Working hours : Monday to Friday | 8.30am to 5.30pm
• Location: Office in Boon Lay-Islandwide
• Salary (commensurate with experience) : Up to $5500 (Basic + $1000 Transport allowance) + AWS + 2 months Variable Bonus (max up to 5 MONTHS BONUS) + 16 days Annual Leaves + Medical Benefits
• Duration : Permanent
• Industry : Refrigerating, Air-conditioning & Ventilation Machinery - MNC

Main Responsibilities:

• Perform project design (including selection and sizing of equipment) and development activities according to customer’s specification.
• Understand scopes of HVAC work (to bid).
• Perform site surveys, site measurements, attend pre-bid walkthrough if need be. Attend tender clarifications/interview as and when required.
• Work with Manager in developing project plan, budget and schedule.
• Coordinate with relevant parties in preparing project proposals, tender submission/clarifications, and contractual documents.
• Regular interaction and follow up to ensure all projects are performed within allocated budget, timelines, and requirements.
• Work and coordinate with sales team to create quotations and follow up for service retrofit jobs.
• Source/liaise/negotiate with suppliers and vendors on quotations and requirements. Compile supplier quotation, assessment of quotations and prepare costing sheet.
• Maintain estimating logs and unit costs for all projects.
• Determine Bill of Quantity
• Any other duties as deemed appropriate.

Requirements:

• Degree/ Diploma in Engineering/Building
• Experience and knowledge in HVAC/ACMV is a must
• Knowledge of different types of HVAC systems and their components
• Ability to read and comprehend mechanical drawings and other construction documents.
• Knowledge of commercial HVAC/ Mechanical Contracting
• Min 2-3 years relevant experience
• Have own vehicle for travelling

As a member of the Advanced Development team, you will lead the charge for new technology and design solutions for BISSELL products. You will be part of a collaborative innovation and advance development team to drive excellence in investigating and delivering new technology and design solutions for features, functions, and performance of components and sub-systems for products developed by BISSELL.

Responsibilities:

• Drive investigations, development and integration of technology and design solutions into BISSELL products
• Coordinate and converge internal and external organization activities to conclude on the technical and financial feasibility of technology and design solution proposals with the stakeholders in the company.
• Contribute to advance technology design knowledge and capabilities in the organization
• Complete analysis, design, and validation of new technology and design solutions ideas to mature readiness for product integration.
• Document and present investigations with clear data driven conclusions and recommendations that include solution value, limits, trade-offs, costs, risks, and effort.
• Engage with Global Product Marketing and Engineering Teams to review and conclude the feasibility of technology and design solutions proposed.
• Support product engineering teams in the integration and implementation of accepted technology and design solutions.

Qualification:

• Ph.D./Master's degree in Mechanical/ Mechatronics Engineering
• Industry experience is preferred but not required in the case of relevant experience gained through research and academic engagements.

Experience:

• Structural design and fabrication of mechanical components and assemblies.
• Design and fabrication of aerodynamic parts in turbomachinery, i.e. fans, rotors and impellers.
• Experience on single stage or multi-stage turbine design is an added advantage.
• Expertise to work with different materials, eg plastic, metal, etc. Technical acumen to explore new materials is desirable.
• Design with CAD Modelling and Design Tools (Experience in Creo will be an added advantage). Ability to read, understand and generate engineering drawings using CAD tools is a must.
• Able to carry out Aerodynamic CFD simulation. Experience with CFD design and meshing of complex assemblies with Ansys Mechanical and Fluent.
• Working knowledge of mechanical test standards and test execution activities related to area of work.
• Working knowledge for mechanical tolerancing and stack analysis.
• Able to work with Product Lifecycle Management tools (Experience in PTC Windchill will be an added advantage)
• Working knowledge on measurement/analysis of thermal profile of high-speed electromechanical devices is an added advantage.
• Working knowledge on design and fabrication of high speed electromechanical and electromagnetic components cooling solutions is an added advantage.
• Business acumen to analyze and gauge the commercial viability and IP feasibility is desirable.

Competencies:

• You must have passion, energy and a natural curiosity for research, technology and design. You associate yourself with the following characteristics.
• Proactive in learning and capability growth.
• Possess an innovation mindset.
• Able to do analytical and conceptual thinking.
• Structured, creative and self-driven in problem solving.
• Effective communication skills, both written and verbal.
• Good planning and stakeholder management skills.
• Approachable and engaging in collaboration work.
• A good team player and able to work well in a cross functional and international team environment.
• Effective at presenting results and recommendations to stakeholders and senior levels.
• Able to independently plan, manage and drive results and commitments.

Be part of a team in creating state-of-the-art Secure Low Power SoC ARM-based SoC/MCU for the Low-End , Mid and High-End performance MCU product line in a IC Design Environment.

Responsible:

• Engage design team and architects to strategies DFT Test plan for SoC top level
• Create DFT test modes, scan architecture, clocking and reset architecture.
• Plan Pin-Muxing and Pad and Boundary scan (BSDL) generation
• Execute JTAG TAP network generation and verification.
• Quality check with Spyglass analysis for scan using spyglass tool
• Execute Scan insertion using DC / Tessent tools
• Deploy Scan constraints development for Atspeed, shift and slow capture mode.
• Generate ATPG pattern generation using synopsys Tetramax tools
• Analyze and report on test coverage metrics to ensure comprehensive testing of designs.
• Implement improvements to enhance test coverage and efficiency.
• Verify No-timing and SDF simulation of ATPG patterns using VCS and NCSim tools
• Implement MBIST MBIST repair and verification using Mentor Graphic Tessent tools.
• Boundary scan verification
• Generate STIL test patterns for tester
• Silicon bring-up and failure debug

Requirements:

• Requires BSc/MSc or PhD in electrical and electronic or Computer engineering
• Requires > 5 years or more of experience in DFT at IP and SoC top level. Proficient at using DC ,tetramax and MG tessent DFT tools
• Tape-out at least 5 chips and tested to pass on tester.
• Requires strong understanding of state of the DFT methodology , flat and hierarchical implement of DFT from IP to SoC top.
• Capable of understanding UPF to enable multiple power domain verification
• Capable of leading, review and guiding younger DFT engineers in their daily tasks
• Able to work in a team with a strong drive to excel
• Able to work independently on a given assignment and work hard to finish on time
• Good written and communication skills