Responsibility

• Responsible for high-performance block implementation (RTL to GDSII).
• Perform block level floor planning, power grid implementation, APR placement, timing optimization, CTS and routing.
• Close the design to meet timing, power budget and area targets.
• Run physical verification flows (DRC/LVS/EM/IR), and implement fixes to meet the requirements.
• Implement ECO’s to address functional bugs, timing and physical verification violations.
• Responsible for the generation and maintenance of block-level STA constraints and performing STA signoff checks.
• Responsible for timing model generation and supporting the successful integration of blocks into SOC.

Qualification

• At least 3 years of hands-on experience in digital-physical design.
• Master’s/Bachelor’s degree in Electrical Engineering with an emphasis in IC design， master's degree preferred.
• Experience with digital Physical design and Static Timing Analysis
• Experience in floor planning and routing.
• Experience in advanced process nodes (5nm).
• Good experience with Synopsys implementation tools (DC, ICC2), and experience with Cadence (Innovus) implementation tool is a plus.
• Experience in Mentor Verification tool, Calibre.
• Proficient in TCL coding, Perl/Python knowledge is a plus.
• Good written and communication skills.
• Bilingual to communicate with associates in China is perferable.

Job Description

- Design, customise and build components and systems for product testing and qualification

- Perform and complete product qualification and tests in accordance with prescribed standards

- Trouble-shoot and resolve technical issues with regard to process and testing

- Collaborate and liaise with internal engineering teams / sub-contractors to ensure timely delivery of project deliverables

- Support management of workshops and laboratories

Job Requirements

- Degree or Diploma in Mechanical / Precision Engineering

- Experience in relevant engineering field

- Proficient in ASTM, BS, ISO, MIL standards

- Proficient in Solidworks

- Familiarity with pneumatics preferred

- Qualification and trained in BizSAFE Level 2 and ISO22301 preferred.

Job description:

• The Design Verification Engineer will be responsible for verification of digital and mixed-signal designs, including systems-on-chip with multiple CPUs, and digital signal processors, security hardware, and other logic for IoT applications.
• The ideal candidate should have demonstrated successful design verification tasks at block, sub-system, and full-chip level.
• Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrating VIP’s, automated test env for randomized testing and score boarding.
• Utilize UVM to create drivers, monitors, predictors, and scoreboards.
• In-Depth knowledge of SoC architecture with AMBA AXI/AHB/APB, DMA’s, Security, clock, and power-gating techniques is required.
• Responsible for verification of block(s) that includes writing tests, assertion, and coverage for a block.
• Create tests to achieve coverage goals while verifying functionality.
• Develop support utilities for verification automation, test bench automation, regression, to improve productivity.
• Develop tests to evaluate power and performance aspects of the design.
• Perform gate-level-simulations and participate in supporting FPGA and Post-silicon bring-up.

Requirements:

• BSEE/MSEE Degree 8-12 years of experience at block, sub-system and full-chip verification.
• Strong in understanding multiple architectures, integrate 3rd party IP’s/VIP’s, have worked with mixed-signal designs with low-power design and verification challenges.
• Experience with System Verilog simulation required.
• Strong understanding/exposure to Design Verification for low-power battery operated designs highly desired.
• C based verification in an SoC environment is required.
• Experience with ARM processor-based designs and low-power design techniques is a plus.
• Languages: SystemVerilog (UVM), Verilog, C/C++, Python, Makefile
• Technologies: ARM SoC (Preferred), AMBA AXI/AHB/APB, DMA, Flow Control, Serial Devices, QoS
• Preferred technologies: MIPI(CSI/DSI), Crypto, OTP, DSP, Low-Power

The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.

Interested candidates may also apply or write in to CS Chua, EA 12C6130/ R1548619 [email protected]. Shortlisted candidates will be contacted for a discussion.

Job Summary: We are in search of a highly motivated and accomplished Senior Research Assistant or Research Associate to join our team and contribute to our ongoing research project "Towards Realistic Deep Learning for 3D Vision". The successful candidate will collaborate closely with our research team, working on the development of ground-breaking algorithms and methodologies for 3D deep learning from heterogeneous data sources such as language and 3D data. This role offers an exciting opportunity to engage in cutting-edge research and have a substantial influence on the field.

Responsibilities:

• Undertake research in the field of realistic 3D deep learning, with a primary focus on pioneering algorithms and methodologies with language-guided 3D scene understanding.
• Design and execute experiments to validate the proposed approaches.
• Analyze and interpret data sourced from heterogeneous inputs.
• Stay up-to-date with the latest advancements in language-guided 3D scene understanding and related fields, and integrate new findings into research projects.
• Prepare research papers for publication in prestigious conferences.

Qualifications:

• A Master degree in computer science, Electrical Engineering, or a related discipline, with a specialization on computer vision, image processing, or 3D reconstruction.
• A strong background in computer vision, machine learning, and 3D geometry.
• Proficiency in programming languages such as Python, C++, or MATLAB.
• Experience with relevant software libraries and frameworks, such as Pytorch, OpenCV, or PCL.
• A solid grasp of mathematical concepts related to 3D computer vision, including geometry, optimization, and statistical methods.
• Good problem-solving and analytical abilities.
• Strong communication skills

We are an education centre looking to hire a art teacher /coach /teaching assistant who

• enjoy working with children of age group 6 to 12 year old
• good with classroom management of classes ranging from 10 to 20 students
• coordinate, organise learning activities during school term and school holidays
• faciliate art lessons, programmes, activities
• able to conduct programmes in fluent English
• well organised and good with basic administration
• proficient in microsoft word, excel, powerpoint and learning apps
• training will be provided
• preferred to have 1 year relevant experience with children in a school, kindergarten or any type of education centre

we have centres islandwide.