As a standard cell design engineer in the Physical Design Group, you will develop your skills working on some of the most sophisticated process nodes targeting the largest foundries. You will contribute to designing our physical IP standard cell offerings for our internal and external customers at leading edge nodes including 5nm and beyond. Work with partners inside the company, as well as our partners in the EDA and foundry space.
Responsibilities:
· Design standard cell circuits and verify them for functionality, performance, and power
· Generate and validate EDA model views of standard cells
Required Skills and Experience :
· 5+ years of relevant circuit design experience (for BSEE)
· 3+ years of relevant circuit design experience (for MSEE)
· Experience with transistor level circuit design using Cadence Virtuoso and circuit simulators such as SPICE, SPECTRE
· An understanding of transistor level device physics and standard cell layout
· Knowledge of power, performance, and area tradeoffs
· An ability to learn a wide variety of industry standard view and modeling formats such as Liberty, Verilog, LEF, NDM, APL, GDS
· Scripting skills in either Tcl, PERL or Python
· Dedication to quality, collaboration, curiosity and continual improvement
