As a Package Design Engineer within the Package Development and Engineering (PDE) organization in Micron Technology, you will provide package definition and designs for advanced semiconductor devices. You will be working with a multi-functional team across several geographies to create package design databases such as package stack-up, simulation, route-study, substrate/lead frame layout, wire bond diagrams, and other design documentation. You will be ensure the completion of design activities within the project schedule and ensure that design outputs are within Assembly and vendor capability.
Responsibilities will include, but are not limited to:
- Conduct feasibility studies for various package options and assess designs for manufacturability and reliability.
- Work closely with multi-functional team to address packaging design challenge in the area of layout, electrical, thermal, mechanical, assembly and reliability.
- Interact with PDE assembly team and external assembly subcontractor partners to recommend package solutions to meet customer and/or market requirements
- Generate and update assembly documents in database. Provide drafting and drawing support for package drawings, interposer drawings, and manufacturing drawings.
- Support package and DFMEA reviews with assembly engineering and subcon teams.
- Support package technology development, including material selection, process development, DOEs, and related activities
- Support package technology development, including material selection, process development, DOEs (Design of Experiments), and related activities.
- Track and drive program milestones to ensure timely development execution.
- Provide design support for thermal/mechanical/electrical simulation analysis.
- Support and contribute to the Global Design, Simulation and Substrate (GDSS) team on continuous improvement efforts such as:Global design alignment activities
Continuous improvement efforts
Package design rules
Package roadmaps
Competitive Analysis review
Requirements:
- Master (preferred) or Bachelor of Science degree in Electrical Engineering or Mechanical Engineering with a minimum of 5 years of experience in semiconductor packaging industry OR PhD graduates in Electrical Engineering
- Candidates must possess a strong design knowledge of high-density (Wirebond + Flip-Chip) packaging architectures, die stack-up, packaging layout optimization.
- Excellent communication skills, both oral and written in English.
- Excellent problem solving and analytic skills.
- Experience with Cadence SIP, APD and AutoCAD software tools is preferred.
- Good understanding of Silicon IP, floorplan and Signal/Power Integrity is a plus.
- Ability to work independently, prioritize and manage numerous projects with minimum supervision.
- A global perspective and the ability to work in a multicultural environment.
Performs semiconductor design engineering assignments including engineering and designing packaging stack-up, layout checking, documenting specifications, modifying and evaluating packaging risk in the areas of electrical, thermal, mechanical and reliability. Reviews package design requirements, define the package stack-up and conduct final design review. Typically responsible for projects, or portions of projects, to design, fabricate, modify, and evaluate semiconductor Packaging.
