Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects.
Staff FPGA Engineer
Summary
You will drive the development and rendering of FPGA images in support of our pre-silicon prototyping environments. In this role, you will work with our SoC design, software development, design verification, and system test teams as our primary internal customers for the FPGA images.
The successful candidate will have experience in RTL design, verification, and FPGA/Prototyping platform creation to support Design Verification, Validation, Software Development and System Test at the pre-silicon phase.
The person in this role must be comfortable in working with RTL in order to provide specialized changes to the SoC database specific to the FPGA development flow. This role will require defining and implementing internal and external FPGA timing constraints to enable repeated delivery of design iterations to the software and validation teams. The candidate will be required to debug RTL designs using FPGA tools, external logic analyzers, and protocol analyzers.
Responsibilities
• Implement and debug FPGA designs on AMD FPGA based prototyping platforms using Xilinx Vivado and ISE tools.
• Implement and debug FPGA designs on a Stratix-10 development board using Intel Quartus prime Pro.
• Support a regression test-suite consisting of system-level test cases to validate updated FPGA builds.
• Assist development teams in reproduction, triage, and debug of issues both pre-silicon and post-silicon
• Define and implement timing constraints.
Requirements
• BSEE or BSCE with 10+ years of SoC design, verification, or related work experience and 8+ years of experience of FPGA design, bring-up, debugging, and verification.
• In-depth knowledge of top-down FPGA development process with recent experience with FPGA-based prototyping on an FPGA development platform.
• Solid experience with defining timing constraints for Static Timing Analysis.
• Some familiarity with Cadence SoC design flow.
• Expertise in both Intel Quartus Prime Pro and Xilinx Vivado suites.
• Solid understanding of the tool flow from RTL to bitstream.
• Some familiarity with programming in C language.
• Familiarity with source code control systems (git) required.
• Familiarity with simulation tools.
• Hands-on lab bring-up experience, debug, and instrument usage.
Interested applicants, kindly send in a copy of your updated resume in WORD document to [email protected] stating your current and expected remuneration together with notice period required to current employer.
You can also contact Vincent Low for a confidential discussion at 6749 4236.
EA Personnel Registration No: R1324700
