Overview:
We are looking for result-driven candidates who can thrive under a fast-pace working environment and possess a strong desire to create an impact in the organization.
Candidates with Full Custom Layout Knowledge and/or Auto-Placement/Routing (APR) domain knowledge and experience are welcome to apply.
Job Responsibilities:
· Implement top quality layout which meet the specifications set forth by designers and layout leads while meeting the project objectives and fast paced milestones
· Diligently perform all physical & reliability verifications (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tape-out flow
· Work closely and communicate effectively with multi-functional teams and multi-site to constantly optimize layout for better power, performance, area and schedule
· Responsible for in-house IP / library developments / Full chip integration
Requirements:
· Bachelor’s degree in Electrical/Electronic Engineering
· Has transistor level knowledge for circuits and device layout structure
· Understands analog layout fundamentals, such as floorplan, device matching, EM and IR
· Strong knowledge in floor-planning techniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing, matching and top-down integration flow
· Proficient in Synopsys/Cadence layout editor and physical verification tools; analytical and skillful in debugging DRC/LVS and all other verifications
· Have a good grasp of DRM of advanced node CMOS technologies
· Team player and effective in cross-team communication and time management
· Strong passion in learning, problem solving, and decision-making skills
· Proficiency in script programming (eg. Tcl, Perl or C-shell) is a plus
