Responsibilities
- Full chip and block level timing constraint development, consistent full chip and block constraint partitioning
- Timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation)
- Analysis of clock domain crossing paths at block and full chip level
- Work with FE/IP teams to drive integration, timing, logical equivalence checking and analysis of various IPs
- Develop/modify/run RTL logic synthesis, formal verification, power intent verification and post-synthesis timing validation flows
- Work closely with chip architecture, design verification, physical design, DFT, and power teams to achieve tapeout success on designs – generally bridging the RTL and place and route
Requirements
- Bachelor’s degree in engineering
- 3+ years of experience working as a synthesis and/or front-end STA engineer
- Experience in ASIC multimode constraint generation, constraint partitioning and timing closure in advanced nodes
- Hands-on experience in industry standard physical synthesis and STA tools
- Experience with clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on synthesis, physical design and timing closure
If you are interested in the position, kindly send your CVs to sean.ho(@)randstad.com.sg.
Please include your availability, expected salary and reason for leaving current job.
We regret that only shortlisted candidates will be contacted. EA: 94C3609 / Reg: R22105422
Applicants must be fully vaccinated or have a valid exemption in accordance with MOM's regulations to allow them to enter the workplace. Applicants may be required to share verifiable COVID-19 vaccination documents or proof of a valid exemption at the point of offer. Randstad Pte. Limited and/or the Client reserves the right to withdraw an offer if the applicant fails to provide verifiable COVID-19 vaccination and/or proof of exemption documents
