The overview
- We are looking for result-driven candidates who can thrive under a fast-pace working environment and having a strong desire to create an impact in the organization
Job Description
- Should have good understanding of basic memory architecture, and memory leaf cell layout creation;
- Should have good understanding of basic CMOS and finfet circuits;
- Experience and familiarity in various physical verification checks like DRC, LVS, ERC, Antenna, Density, ESD, LUP, EM, IR, etc;
- Understanding and working knowledge of good layout practices (matching, etc), especially in advanced process nodes, like 7nm, 5nm, 3nm etc, is preferred;
- Good understanding of deep sub-micron and DFM issues in layout design (WPE, LOD effects, etc.);
- Responsible for the development of memory layouts in advance CMOS and finfet processes;
- Perform physical verifications of different memory types, from bottom cells to top hierarchy;
- Undertake the assignments independently or in a team;
- Work closely with memory design engineers and memory compiler engineers to ensure highest quality memory layouts.
Requirements
- Min Diploma / BS or above with major in Electrical and Electronic Engineering / Electronic Engineering majoring in Microelectronics
- Minimum 3 years working experience in Memory Layout Design (SRAM, EFUSE, Via-ROM, TCAM, etc.);
- Proficient with Synopsys Laker/Custom Compiler, or Cadence Virtuoso;
- Familiar with Mentor Graphics Calibre, and Unix environment;
- Bachelor’s Degree/Diploma in Electrical/Electronic Engineering or equivalent
Next Step
- Prepare your updated resume (please include your current salary package with full breakdown such as base, incentives, annual wage supplement, etc.) and expected package.
- Simply click on 'Apply here' or email to [email protected] to drop your resume
- All shortlisted candidates will be contacted.
