JOB DESCRIPTION
-Work on IP developments, Perform Verilog/SystemVerilog RTL design to meet product specifications and requirements；
-Work on SoC architecture discussion and optimization with architect and SW Engineer; SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;
-Work on SoC floorplan with architect and APR; SoC timing constraints and review support; SoC DFT support; SoC verification plan and SoC verification support
-Post silicon Debug and support.
JOB REQUIREMENTS
· Bachelor’s or master’s degree in electronic engineering with 3-5 years ASIC design experience.
· Experience with ASIC design flow
· Experience in RTL coding, RTL and gate-level simulation, logic synthesis, static timing analysis, timing closure and verification
· Experience in video processing and video analytics is a plus
· Passionate and strong in general programming is a plus
· Good understanding of DFT
· Familiar with UNIX/ Linux environment and scripting
· Good communication and interpersonal skills
· Strong analytical and problem-solving skills
