You are our digital circuits professional. You will work with the technical team to design and implement high-performance digital circuits on FPGA or ASIC and be responsible for the entire FPGA build flow from RTL code to verification and timing closure. You are also expected to bring-up, test and verify the final hardware product, together with the product team.
Responsibilities
- Design and implementation of high-performance digital circuits on FPGA or ASIC
- Prepare microarchitecture design based on system specifications and architecture documentation
- Follow through the entire FPGA build flow to perform the various front-end tasks such as RTL coding, synthesis, test and verification and timing closure
- Work closely with hardware design engineers to define I/O interfaces for FPGA and ASIC hardware systems
- Work closely with software design engineers to define register mappings for SoC systems
- Perform quality coverage-driven verification of the design using UVM or other equivalent methodology
- Prepare design documents and test plans
- Work closely as a team to perform bring-up, test and verification on final hardware product
Requirements
- Degree holder (Electrical/Electronics/Computer) with minimum 2 years of relevant working experience in FPGA hardware such as Altera, Xilinx or Lattice
- Strong proficiency and interest in digital circuit design
- Proficient in at least one RTL language such as VHDL or Verilog
- Familiar with FPGA build flow from design entry to synthesis, place and route, timing constraints and timing closure
- Familiar with development, integration or testing of high-speed data interfaces such as Ethernet, PCIe or USB
- Hands-on experience in FPGA debugging tools such as Vivado ILA and Quartus SignalTap
- Good problem solving and failure analysis skills
- Experience in board bring-up and hardware troubleshooting
- Familiar with programming languages like C/C++ and scripting languages like Python/Tcl
- Familiarity with or keen interest in learning ASIC related front-end tasks such as synthesis, timing analysis and logic equivalence check
- Familiar with or keen interest in learning development of UVM test-benches to perform functional simulations on module/system level RTL designs
- Familiar with SoC hardware development
- Singaporeans only
