Responsibilities:
✅Perform IC physical design development of company products
✅Tech file library preparation, full chip floor-planning, clock tree synthesis, place & route, RC extraction
✅Work with front-end to achieve timing closure and optimize power
✅Perform physical verification (LVS/DRC/ERC/Antenna)
✅Perform design revision (design ECO)
✅Interface with foundry for tapeout-related activities
Requirements:
- Degree & above in Electrical or Electronic Engineering
- At least 3 years experience in ASIC flow layout design
- Experience from design to tape-out are essential
- Experience in using EDA tools from Cadence, Synopsys
- Knowledge and working experience in any following:
-Digital and mixed-signal design
-USB interface products
-Knowledge in connectivity technology such as USB, UART, SPI, I2C
-Project Management
Interested applicants, send in your updated resume by clicking “Apply Now”
Lin Weikang
Registration Number: R21102570
EA License Number: 19C9998
Workstone Pte Ltd
