Job Responsibilities:-
- Responsible for toplevel and blocks whose complexity is at the limit of current tool capacity
- Responsible for all aspects of physical implementation, include floor-planning, physical synthesis, clock-tree synthesis, parasitic extraction
- Responsible for IO ring design and bump implementation, meeting ESD, EMI and SSO requirements
- Implementation of Low power layout methodology (multiple switchable power domains, level shifter)
- Execution of static and dynamic drop, ramp up analysis using Redhawk
- Perform static timing analysis to handle complex timing closure
- Work with other design engineer in Synthesis, Design for Testability, STA/timing closure and Equivalent checks to resolve issues
Job Requirements:-
- Master’s/Bachelor’s Degree in Electrical/Electronics Engineering with an emphasis in IC design with minimum 5 years or more related experience
- Experience with complex Low Power SOC in 16nm/7nm, 5nm is a plus
- Good experience with Cadence or Synopsys implementation tool (Tempus, Innovus, DC, ICC2, Fusion Compiler), experience with Cadence implementation tool is a plus
- Experience in Mentor Verification tool, Calibre
- Experience in Redhawk
- Proficient in TCL code, python knowledge is a plus
- Able to work in a multi-cultural team with a strong drive to excel
- Good written and communication skills
Location: Next to Bendemeer MRT
Interested candidates may submit detailed CV with the following info:-
- Current salary, including AWS or Variable Bonus
- Expected salary
- Availability
