R&D engineer position available in design and physical implementation of high performance System-On-Chip ASICs.
- Key competencies required are: Working experience leading team in physical design implementation of large ASICs (100 to 400 million gates complexity).
- Demonstrated ability in providing technical support to customers and managing customer working relationship.
- Demonstrated strong technical hands-on competency in using leading edge physical design EDA tools in projects.
- In-depth CPU architecture/algorithm working knowledge and related physical design implementation knowledge highly advantageous.
Utilize commercial and in-house EDA tools for the design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm process technologies.
Opportunity to participate in innovation, design flow and methodology development to address challenges of designing into deep submicron processes and state-of-the-art ASIC design for computing and networking products
Qualifications / Requirements
- Degree, Masters or PhD in Electrical/Electronics/Computer engineering with 5 years or more experience in a relevant field.
- Familiarity with one or more VLSI design tools for Place&Route, Verilog Simulation, DRC/LVS Physical Verification, Static Timing Analysis and Power Integrity
- Experience in Perl & Tcl Scripting languages 3. Proficiency in UNIX/Linux is advantageous.
