Responsibilities
· Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
· Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
· Verify Logic at ISP level and Digital System level
· Optimize Design for less gate count and low power consumption
· Drive ISP Design activities in close collaboration with ISP Algorithm Team, ISP Design leaders in other sites, and Digital System Design Team
· Leading, supervising and mentoring a team of RTL design engineers
Requirements
· Minimum MSEE, or BSEE, or equivalent, plus 7+ years of Digital Design and verification related experience
· 3+ years project management / people management experience / skill
· Experience / knowledge in CMOS Image Sensor and image signal processing (ISP)
· Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
· Ability to lead teams and collaborate effectively with people in different functions
· Strong time management skills to ensure timely completion of deliverables
· Good communication and interpersonal skills
· Result oriented and embrace change behaviours
