Overview
We are seeking a talented and motivated AI compiler Engineer (AI Sub-system) to join our R&D team to own, define, and drive exploration and design of our next generation runtime software involving multi heterogeneous devices in high performance computing (HPC) SoCs.
Our division’s mission is to use the latest AI and cloud technologies to develop the best AI inference for advanced driver safety engineers building self-driving vehicles and other high performance compute products. Renesas is the leading automotive electronics supplier globally, and this is a rare opportunity to develop the infrastructure required to deploy our AI software to the billions of devices we ship to customers every year.
You will join our newly formed AI & Cloud Engineering organization of around 100 software engineers. Due to strong demand for our AI-related products we are planning to triple in size in the next three years, so there is lots of room for you to help us grow the team together while remaining small.
Our team’s key locations are Tokyo, London, Paris, Dusseldorf, Beijing, Singapore, Ho Chi Minh City, and other metropolitan areas, but you can also join fully remotely from other locations globally or get our support to relocate to our key hubs such as Tokyo.
Responsibilities
- Participate and lead in the software architecture design of the runtime software across multi-device and heterogeneity.
- Apply code optimization techniques, ensuring efficient and optimized performance of the runtime software components.
- Deliver architecture specifications to developers and articulate them effectively across stakeholders ranging from toolchain, system and hardware teams, and to technology leadership.
- Collaborate with silicon and platform bring-up to verify and debug the AI sub-system and its delivered performance
Qualifications
- Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or related field; Ph.D. is a plus.
- 10 years of embedded software design and development on SoCs and/or ASICs.
- Great coding skills in C/C++.
- Great knowledge of SW architectural patterns (layered/plugin/event-driven/ microkernel/etc).
- Good knowledge of SDLC.
- Good knowledge of RTOS and/or Linux OS.
- Good knowledge of multi-thread and multi-process software design and debugging.
- Experience with embedded system involving multi-core CPU/DSP.
- Experience with heterogeneous multi-device system involving GPU/NPU/FPGA.
- Knowledge of debuggers (LLDB, GDB) and profilers on heterogeneous hardware system.
Preferences
- Experience with Python is a plus.
- Experience with ARM and/or RISCV ISA is a plus.
- Knowledge of Linux kernel and driver development is a plus.
- Knowledge of CNN and common NN operators/layers like Conv2D, BatchNorm, etc is a plus.
- Knowledge of internal of inference engines like TFLite, OpenVINO runtime, ONNX runtime, TVM runtime, etc is a plus.
- Knowledge of JTAG debugger and bare-metal bring-up is a plus.
- Knowledge of high performance domain-specific languages (SYCL/CUDA/OpenCL) is a plus.
- Knowledge of PyTorch or TensorFlow is a plus.
- Knowledge of just-in-time compilation techniques is a plus.
