- Implement IC design development of products, Logic Synthesis and Static Timing Analysis
- Manage DFT related activities - Scan Insertion, ATPG, Pattern Validation
- Assist in debug & correct any functional issues found in taped-out devices
Requirements:
- Degree in Electrical/Electronics Engineering or equivalent
- At least 5 years of digital IC design experience using EDA tools (Cadence, Synopsys)
- Proficiency in Verilog HDL and VHDL RTL design, Logic Synthesis, DFT, ATPG, Timing Closure
If you are keen to apply for the position, kindly email your detailed resume in MS Word to [email protected]
Please note that only shortlisted candidates will be notified.
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EA Licence: 19C9701
Registration: R22111604