Job Description
- Works with the front-end design team to complete the chip floorplan , clock architecture, and powerplan .
- Takes charge of the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tapeout.
- Researches the physical design methodology of advanced process nodes, and builds an automatic physical design platform.
Position Requirements:
- Holds a bachelor's degree or above in electronic engineering, microelectronics, or computer science.
- At least five years of work experience in the digital backend design field. Hands-on project experience is required. Tapeout experience at advanced technology is preferred.
- Those with experience in TCL , Perl or Python script development and familiar with EDA tool design will be plus.
Interested candidates may apply through the application system. We regret to inform only shortlisted candidates will be notified.
EA License No. 01C4394 • RCB No. 200007268E •Derrick Tiew Yong Han EA Registration No. R1877971
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