Job Responsibilities:-
- Collaborate with concept team on frontloading activities to develop and review high level specification
- Develop micro-architecture of digital blocks/modules
- RTL design using VHDL/Verilog HDL coding
- Perform quality checks e.g. Linting, CDC, code coverage
- Collaborate with functional verification team on test plan and debug/fix failing test cases
- Provide synthesis constraints and involve in DFT insertion, timing closure and area optimizations
- Pre/post-silicon system validation debug and bring up support
- Prepare micro-architecture document for detailed design reviews with project team
- Prepare task list, effort estimate and commit to schedule
Job Requirements:-
- Degree or Master's in Electronics and Communication Engineering or equivalent with focus on Digital Design
- Minimum 8 years of ASIC or SoC/IP design experience
- Hands-on experience in micro architecture development, RTL coding, linting, CDC, constraining timing paths
- Basic understanding on verification and test cases development
- Pre/post-silicon system validation debug and bring up support
- Familiarity with Synopsys and Cadence EDA tools for simulation and quality checks
- Know-how of low power techniques and methodology
- System knowledge in communication domain and its interface protocols
- Knowledge of packet processing, Ethernet interface protocols and standard , clock and reset and CPU subsystem
- Strong ability to use analytical skills to solve complex problems
- Good communication and interpersonal skills
- Experience to work with cross functional and multi-site teams
Location: Next to Bendemeer MRT
Interested candidates may submit detailed CV with the following info:-
- Current salary, including AWS or Variable Bonus
- Expected salary
- Availability
