Position Overview:
The Design Manager will oversee the development of micro-architecture for ISP and CV related algorithms. They will manage a team of design engineers, guide RTL design using Verilog/System Verilog coding and HLS tools like Catapult, and ensure metrics such as power, performance, and area are met. They will drive verification signoff in collaboration with architects and DV Engineers, and manage FPGA tasks including emulation, validation, and debugging.
Responsibilities:
- Oversee and guide the development of micro-architecture for ISP and CV algorithms.
- Manage a team of design engineers and ensure effective RTL design using Verilog/System Verilog and HLS tools (Catapult).
- Ensure the analysis and optimization of metrics like power, performance, and area.
- Drive verification signoff with architects and DV engineers.
- Oversee FPGA tasks including emulation, validation, and debugging. Qualification/ Requirements:
- Education: Bachelor/Master’s degree or above in Electrical/Electronics/Computer Engineering is required.
- Experience: Minimum 8 years and above of experience in ASIC design. Expertise in image signal processing projects is beneficial.
Technical Skills:
- Advanced proficiency in HDL languages (Verilog, System Verilog).
- In-depth knowledge of all phases of ASIC frontend design and sign-off.
- Extensive experience in image/vision/video data processing or algorithm acceleration.
- Proficiency in scripting languages like Python, Perl, or C/C++..
- Soft Skills: Strong leadership, management, teamwork, and communication skills.
- Exceptional analytical skills, strategic planning abilities, and the capability to lead complex projects and teams.
