About the team:
Desiweminer specializes in end-to-end customization and comprehensive control across the entire process, from ASIC chip design to miner production, ensuring timely delivery of cutting-edge technological products. Our focus lies in the development and manufacturing of blockchain-oriented ASIC chips and crypto miners. With expertise in creating proprietary ASIC chips and crypto mining solutions, we cater to large-scale industrial mining needs, offering unparalleled time-to-market efficiency.
Position Overview:
We are seeking a highly skilled Senior IC R&D Engineer with extensive experience in RTL2GDS, EDA tools, STA analysis, advanced technology signoff, and low power methodology. Preferred candidates should have experience in successful tape-outs of ultra-low voltage chips, large-scale chips, and complex IPs.
Key Responsibilities:
- Lead and manage the complete physical implementation process of digital circuits from RTL to GDSII.
- Utilize EDA tools such as INVS, FC, PT, PX, RH, and Calibre for design and verification.
- Conduct thorough STA analysis and ensure robust timing closure.
- Implement and optimize the DC or FC integrated process.
- Oversee TOP PR/PI/PV/BUMP planning and ESD planning.
- Adhere to and implement advanced technology signoff standards.
- Drive successful tape-outs of ultra-low voltage chips, large-scale chips, and complex IPs.
- Develop and apply low power design methodologies and processes.
- Perform detailed power analysis and optimize PPA (Performance, Power, Area).
- Collaborate with cross-functional teams to achieve project milestones and objectives.
How You Will Stand Out:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Proven experience in the full physical implementation of digital circuits (RTL2GDS).
- Demonstrated experience in successful tape-outs of ultra-low voltage chips, large-scale chips, and complex IPs under advanced technology.
- Experience in planning and executing ESD strategies.
- Familiarity with DC or FC integrated process.
- Experience in TOP PR/PI/PV/BUMP planning and ESD planning is preferred.
- Familiarity with advanced technology signoff standards is preferred.
- In-depth knowledge of low power design methodologies and power analysis processes.
- Experience in PPA optimization is highly desirable.
- Proficiency with EDA tools such as INVS, FC, PT, PX, RH, Calibre, etc.
- Strong knowledge of STA analysis methods and processes.
- Deep understanding of power analysis and low power design techniques.
- Strong problem-solving skills and attention to detail.
- Excellent communication and teamwork abilities.
What you will experience working with us:
- A culture that values authenticity and diversity of thoughts and backgrounds;
- An inclusive and respectable environment with open workspaces and an exciting start-up spirit;
- A fast-growing company with the chance to network with industrial pioneers and enthusiasts;
- Ability to contribute directly and make an impact on the future of the digital asset industry;
- Involvement in new projects, developing processes/systems;
- Personal accountability, autonomy, fast growth, and learning opportunities;
- Attractive welfare benefits and developmental opportunities such as training and mentoring.
Desiwe is committed to providing equal employment opportunities by country, state, and local laws. Desiwe does not discriminate against employees or applicants based on conditions such as race, color, gender identity and/or expression, sexual orientation, marital and/or parental status, religion, political opinion, nationality, ethnic background or social origin, social status, disability, age, indigenous status, and union.
