Job Responsibilities
1. Responsible for UCIe and other chiplet interface IP competitive analysis, roadmap planning and specification formulation;
2. Responsible for the design and implementation of PHY, adaptation layer and protocol layer IP architecture for chiplet interfaces;
3. Responsible for the development and delivery of inhouse-developed chiplet interface PHY IP and achieving corresponding PPA indicators;
4. Assist the back-end team to complete the physical implementation of PHY IP and timing closure;
5. Responsible for the design and implementation of test pieces, packaging design, test board design, post-silicon bring up and testing related work.
Job Requirements
1. More than 10 years of experience in High-Speed Interface IP design and successful tape-out;
2. More than 5 years of experience in areas related or similar to UCIe IP architecture design such as PCIe/CXL, AXI, AHB, APB and DDR;
3. Successful development experience of advanced interface technology IP;
4. Familiar with chiplet IP market and competitive landscape, and has rich experience in product road mapping and product definition;
5. Those who are familiar with standards such as UCIe, PCIE/CXL, AXI, AHB, APB and DDR are desired;
6. Candidates with experience in UCIe and other subsystem development, tape-out, debugging and successful mass production will be given priority;
7. Have good communication skills, high sense of responsibility, strong sense of delivery, and excellent team spirit.
