Responsibilities
- Advanced low-power physical design/integration flow development
- Synthesis, floor planning and place & route
- Full-chip floor planning and layout
- Power network design and analysis
- Support signoff timing closure, power integrity, and signal integrity
- Physical Verification using DRC, LVS
Qualifications
- Degree or related field required
- 3+ years industry experience required
- Experience on high performance and low-power physical design
- Experience on deep sub-micron process technology (14nm and below) taped outs
- Experience on floor planning, power network design, power optimization/analysis, clock-tree design, static-timing analysis, DRC, LVS
- Excellent interpersonal and communication skills
- Experience on using Perl, TCL, Make, and other script languages
- Experience on Synopsys or Cadence tools (Design Compiler, IC Compiler, StarRCXT, Primetime, Innovus)
- Experience on Mentor or Synopsys verification tools (Calibre, ICV)
