Responsibilities
- Work with IC designers and chip leads to architect, design and optimize custom layout of standard cells.
- Layout design of analog circuit blocks with attention to matching and minimizing parasitics in the layout.
- Physical Verification using DRC, ERC and LVS.
Qualifications
- BSEE or higher required
- 5+ years industry experience required
- Strong analog layout design skills
- Expert-level knowledge with Cadence Virtuoso tool suite
- Expert-level knowledge with Mentor Graphics Calibre
- Strong experience in advanced node IC layout. Knowing GAA is preferred.
- Able to work independently on challenging problems
- Understand layout considerations for device matching, coupling and noise isolation
- Excellent communication skills (both oral and written) arerequired
- Able to study custom circuit simulation/characterize library/custom circuit design for future work. Having one of those capability is preferred
