Design
Perform RTL design, synthesis, and optimization for timing, area, and power to meet IP specifications and requirements.
Work closely with system/ASIC architects to understand system requirements and contribute to architectural decisions.
Work with system and software teams on pre-silicon FPGA verification.
Verification
Develop and maintain verification environment for IP modules and SoC level using UVM methodology.
Perform front-end verification using UVM methodology.
Common
Support system and software team on post silicon evaluation.
Continual design automation for better efficiency.
