Job Responsibilities:
- Architect and plan competitive analysis and roadmap for 112G LR SerDes PHY IP, and formulate specifications.
- Design and implement PHY IP architecture for 112G LR SerDes.
- Develop in-house 112G LR SerDes PHY IP, ensuring achievement of PPA (Power, Performance, Area) indicators.
- Collaborate with the back-end team to complete physical implementation of PHY IP and achieve timing closure.
- Design and implement test chips, package design, test board design, and oversee post-silicon bring-up and testing.
Job Requirements:
- Over 10 years of experience in SerDes PHY IP design with successful tape-outs.
- More than 5 years of experience specifically in SerDes PHY IP architecture design.
- Successful development experience in advanced technologies for 112G LR SerDes or higher.
- Deep familiarity with the SerDes and high-speed interface PHY IP market, competitive landscape, and extensive experience in product road mapping and definition.
- Preference for candidates with experience in similar IP design, subsystem development, tape-out, debugging, and successful mass production.
- Strong communication skills, high sense of responsibility, commitment to delivery, and excellent team collaboration skills.
Please be informed that if you are interested in applying for a position, please email your resume in either Word or PDF format to [email protected]. In your resume, kindly include the following details:
- Current Salary:
- Expected Salary:
- Availability:
- Reason for leaving your current job:
Thank you for your application. Please note that only shortlisted candidates will be contacted for further consideration.
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EA (23S1595/R23116355)
