Verification Engineer

Job Responsibilities:

1. Develop module level and system level verification plans based on design spec;
2. Build verification environment using UVM infrastructure ;
3. Define reasonable functional coverage according to the verification plan, add test vectors, and meet the requirements for functional coverage and code coverage;
4. Complete the verification tasks of each stage of the chip, meet the verification requirement of each node, and successfully stream the chip;
5. Complete the verification report of the responsible module and pass the verification review.

Job Requirements

1. Master's degree or above, major in microelectronics, electronic engineering, integrated circuit, etc;
2. Deep understanding on ASIC design and verification flow;
3. Excellent knowledge of verification methodology like system Verilog, UVM;
4. Ability to analyze and solve problems independently;
5. Master at least one script development language: python/perl/tcl/shell;
6. Experience in chip verification for specific projects is preferred, while experience in UVM verification is preferred.