Position Overview: The Senior Design Engineer will lead the development of micro-architecture for ISP and CV related algorithms. They will utilize RTL design using Verilog/System Verilog coding and HLS tools like Catapult, and analyze metrics such as power, performance, and area to meet key objectives. They will also drive verification signoff in collaboration with architects and DV Engineers, and provide extensive support for FPGA tasks including emulation, validation, and debugging.
Responsibilities:
- Lead the development of micro-architecture for ISP and CV algorithms.
- Perform RTL design using Verilog/System Verilog and HLS tools (Catapult).
- Analyze and optimize metrics like power, performance, and area.
- Drive verification signoff with architects and DV Engineers.
- Lead FPGA tasks including emulation, validation, and debugging. Qualification/ Requirements:
- Education: Bachelor/Master’s degree or above in Electrical/Electronics/Computer Engineering is required.
Qualification/ Requirements:
- Education: Bachelor/Master’s degree or above in Electrical/Electronics/Computer Engineering is required.
- Experience: Minimum 3 years of experience in ASIC design. Expertise in image signal processing projects is beneficial.
- Advanced proficiency in HDL languages (Verilog, System Verilog).
- In-depth knowledge of all phases of ASIC frontend design and sign-off.
- Extensive experience in image/vision/video data processing or algorithm acceleration.
- Proficiency in scripting languages like Python, Perl, or C/C++..
- Soft Skills: Excellent leadership, teamwork, and communication skills.
- Additional Notes: Strong analytical skills and the ability to lead complex projects independently and within teams.
