Our client is a leading startup in the semiconductor field and a leader in designing low-power microprocessors. The Singapore office houses the Regional Technology Design Center which will be driving the growth and innovation for its products.
R&D Senior Staff Technology Development Engineer
(Newly created position in Singapore – reports to CTO office)
Responsibilities:
We seek a skilled and experienced Design Technology Engineer with strong expertise in FinFET circuit design. As part of the Design Technology team reporting to the CTO, you will be a domain expert looking at advanced technology projects in the field of custom circuit design, simulation as well as standard cell libraries characterization projects. Your primary responsibility will be to characterize and optimize standard cell performance and design custom circuits and simulations. You will work closely with cross-functional teams to ensure the standard cell libraries' quality, reliability, and efficiency.
Responsibilities
Circuit Design (50%)
· Investigate, plan, and design and productize novel sub-threshold and near-threshold circuits and other related low power circuit techniques (e.g., adaptive body biasing, adaptive clock distributions, level shifters, customized standard cells, specialized memory structures, PDN modeling etc.).
· Validate and refine low power circuit design techniques as part of a team that is building standard cells in advanced nodes (e.g., 12nm and beyond).
· Driving new standard cell circuit design concepts, modeling, simulation and layout optimization efforts to improve PPA.
Characterization (50%)
· Drive cell characterization, QA flows, and setup collaterals for standard cells, memory, and IOs
· Characterize and optimize standard cell libraries for FinFET technology, focusing on performance, power, and area metrics.
· Collaborate with circuit designers and layout engineers to define library requirements and ensure adherence to design rules and guidelines.
· Develop and execute standard cell library characterization test plans, including timing, power, noise, and reliability analyses.
· Conduct transistor-level simulations and circuit-level measurements to validate and optimize standard cell performance.
· Perform detailed characterization data analysis, identify deviations and anomalies, and propose corrective actions.
· Work closely with process engineers to understand and mitigate process variations that may impact standard cell library performance.
Requirements
· Bachelor’s degree in electrical engineering or a related field with minimum of 10-15 years of experience in standard cell library characterization, custom circuit design, and simulation, with a strong emphasis on FinFET technology, is required.
· You should be familiar with industry-standard EDA tools for transistor-level and circuit-level simulations, such as Cadence or Synopsys and Cadence Virtuoso Liberate/LV/Mx/Trio
· Familiarity with circuit and layout design, static timing analysis (STA), and power analysis methodologies.
· Solid understanding of FinFET technology and its impact on standard cell library design and characterization.
· Experience characterizing standard cell libraries for advanced process nodes (e.g., 16nm, 12nm, 6nm, or below) is highly desirable.
· Knowledge of standard cell architectures, design rules, and layout considerations.
· Strong analytical skills and attention to detail for data analysis and problem-solving.
Interested applicants, kindly send in a copy of your updated resume in WORD document to [email protected] stating your current and expected remuneration together with notice period required to current employer.
You can also contact Vincent Low for a confidential discussion at 6749 4236.
EA Personnel Registration No: R1324700
