THE ROLE:
The successful candidate will collaborate closely with internal teams including Design, Architecture, Foundry Technology Development (FTO), and NPI teams. The role requires deep involvement in advanced CMOS technology nodes (3nm/2nm) and 3D heterogeneous packaging process development, semiconductor characterization, and defining process technology for products.
THE PERSON:
The candidate will be tasked with leading the design, development, and characterization of 3D test chips for FPGA applications. This includes overseeing all phases from conceptualization, desing to implementation.
KEY RESPONSIBLITIES:
- The candidate will assist in the design and development of chip-on-wafer stacked device technology, which includes working on ESD and LUP protection, data analysis, process and yield characterization in collaboration with foundry partners and internal teams.
- The candidate will provide independent support to internal teams for product debug in 2nm/3nm processes, process optimization, and new product introductions, including support during tapeout phases.
- This position requires a proactive approach and the ability to work independently, while also collaborating effectively within a team environment.
PREFERRED EXPERIENCE:
- Experience: Minimum of 5 years in IC design with strong problem-solving skills.
- Specialized Knowledge: Preferred background in advanced CMOS processes and/or 3D device technology
ACADEMIC CREDENTIALS:
- Educational Qualification: Bachelor's degree required; Doctoral degree preferred.
- Field of Study: Degree in Electrical Engineering, Materials Science and Engineering, or related.
LOCATION:
Singapore
