Job Responsibilities:
- Participate in chip architecture design, module partitioning, and performance optimization.
- Responsible for the RTL design of critical modules.
- IP Integration and simulation of IPs such as PLL, EFUSE, SPI, UART etc.
- PCIE subsystem integration and system-level simulation.
Requirements：
- Bachelor's degree or above in Electronics, Computer Science, or related fields.
- Proficient in Verilog language and familiar with relevant EDA tool software.
- Experience in IP integration, with successful tape-out experience, is a plus.
- Excellent interpersonal and communication skills.
