Responsibilities:
- Responsible for RTL Coding, Integration and Synthesis and micro-architecture development phases
- Responsible for macro defining specification, testing and verification of the IP components.
- Perform RTL-level design, including micro-architectural, of the digital portions of the IP architecture
- Work closely with methodology, PD teams to implement RTL design into GDSII.
- Drive design closure thru synthesis, static-timing analysis, logical equivalency checking. Help improve flows and scripts for such tasks.
- Support post-silicon product bring-up and debug, and sign-off on test-plans and characterization reports.
- To provide timing constraints and work with PD teams to ensure RTL meets timing.
- To work with Defect Team to improve test coverage.
Requirements:
- Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, Information Systems, Engineering, Science or related studies.
- 5 to 8 years of experience in RTL coding, integration and synthesis, preferably with strong understanding of RTL verification flow and environments (e.g., OVM, hardware modeling, assertions, parameterized / configurable design).
- Strong debugging, programming and scripting skills (such as C, C++, Perl, Python, TCL and etc)
- Thorough knowledge of chip architecture with at least 1 year’ experience in design and micro-architecture development phases.
- Good understanding and working knowledge in other domains like DV and DFT, timing closure.
- Able to provide timing constraints and work with PD teams to ensure RTL meets timing.
- Advantageous if you have knowledge of SoC Design Process and wireless communications systems and standards, including LTE (FDD/TDD) and UMTS.
