THE ROLE:
The product verification team is seeking a DFT engineer to join exciting career on Scan, MBIST, iJTAG test development of latest 7nm MPSoC (Multi Processor System on Chip) products and beyond. The IPs range from ARM based Processor to critical IPs which provide automotive, data center, machine learning and high-speed communication solutions. You will work closely with designers to make sure DFT structures are correctly inserted, with test engineers to make sure ATE test programs can be generated from the DFT (ATPG, MBIST) tools, with product engineers to make sure scan/mbist production test can run seamlessly and stable, and with yield engineers to debug and root-cause failures/defects. You will also be creating RTL design utilizing FPGA fabric resources to build communication logic for stimulus and response delivery between device and ATE.
THE PERSON:
We are looking for candidate with strong desire to learn and explore new engineering ideas. Be able to overcome challenging problems, have strong analytical and problem-solving skills, be willing to learn and ready to take on problems. Strong DFT skills will be put to good use. Successful engineer will interact with many internal and external engineering teams taking new project from conceptual to full production phase.
KEY RESPONSIBILITIES:
- Work closely with design team and make sure DFT structures are correctly inserted.
- Responsible for developing, implementing and verifying DFT schemes on hard-IPs in FPGAs.
- Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault models.
- Responsible for testing other parts of the design, including memory, mixed-signal, I/Os, custom LBISTs & MBISTs, 1149.1 JTAG and IJTAG.
- Responsible to develop Firmware driven cost-effective test strategies/methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench/ATE.
- Collaborate closely with the New Product Introduction and Test/Product teams to ensure timely delivery of robust test patterns, and manage debugging of pattern issues on bench/ATE to root cause the problem.
- Assist in Diagnosis and Yield enhancement through product lifecycle.
- Develop an adaptive and cohesive team to take up any challenging tasks entrusted by management.
PREFERRED EXPERIENCE:
- Strong knowledge of Scan architecture, Scan compression and Memory testing techniques.
- Experience in creating and implementing complex chip-level DFT architecture.
- Experience in DFT implementation including Scan and Scan Compression at IP and SoC level.
- Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
- Proficient in logic design using Verilog and experience in synthesis and STA.
- Experience in developing test benches and simulation in RTL/GATE/SDF environments.
- Experience in MBIST/BISR insertion, simulation is a plus.
- Knowledge of FPGA synthesis and design flow is a plus.
- Experience with post-silicon debug and bench setup is a plus.
- Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc.
- Good communication skills, works well in a group environment that spans across continents.
ACADEMIC CREDENTIALS:
- BS or MS in Electrical/Electronic/Computer Engineering with 5+ years of experience.
- Prior experience as DFT engineer.
LOCATION:
Singapore
