What you'll do:
- Develop and oversee the verification plan in collaboration with design and concept engineering teams.
- Implement or modify SoC test cases as per the plan.
- Perform RTL and gate-level simulations, ensuring functional and code coverage closure.
- Ensure the quality of the test suite using tools such as Certitude.
- Debug test failures in RTL and gate-level simulations.
- Track issues and bugs, working with concept and design engineering to resolve them.
- Conduct RTL design using VHDL (Very High-Speed Integrated Circuit Hardware Description Language).
What you'll need:
- Bachelor's or Master's degree in Electrical/Electronic Engineering.
- 5 to 7 years of relevant experience in design and verification
- Experience with Formal Verification and Formal Equivalence Check is essential.
- Proficiency in Python programming is required.
- Required Skills: System Verilog and UVM
- Prior experience/knowledge in in SoC Verification and Formal Verification.
