Staff / Senior Engineer (IC Verification)

Digital IC Verification

• Develop and maintain verification environment for IP modules and SOC level using UVM methodology.
• Write, review and implement verification plan.
• Create and debug test cases.
• Perform code coverage analysis on IP modules and SOC level.
• Continuous improvement of the verification flow.

Additional responsibilities:

a) Any reasonable task assigned by management and deemed to be within the individuals’ capabilities to ensure smooth running of the business.

b) As this is an evolving business, ongoing change is an integral part of the position. Management will liaise with the individual on any fundamental change to work practices. The individual is required to embrace and adopt any change to working practices.

Knowledge and skill requirements:

• Degree/Master in Electrical/Electronic Engineering
• 5 years or above experience in digital IC verification. Staff level will be considered for engineer with more years of experiences.
• Working experiences from design to tape-out are essential
• Experience in system Verilog and UVM verification methodology
• Experience in using EDA tools from Synopsys or Cadence
• Knowledge and working experience in one or more of the following is a plus:

1. Digital and mixed-signal design
2. Microcontroller and graphics processor products
3. Knowledge in connectivity technology such as USB, UART, SPI, I2C, AHB.
4. Embedded programming using C language.

Working Conditions:

- Working conditions are normal for an office environment.

- Work requires willingness to work a flexible schedule.