As a DDQA (Development and Design Quality Assurance) Backend of Line Reliability Senior Engineer, you will be primarily responsible for developing and optimizing quality and reliability criteria related to Metal Interconnects and Wafer-to-Wafer Bonding (W2W) process for the next generation of Micron's memory parts in the Global Quality Team. You will also be required to identify, diagnose, and resolve BEOL metal interconnects and W2W bonding assembly process related problems by applying failure analysis, FMEA or 8D methodology. In this position, you will be working in a highly collaborative atmosphere, interacting with various groups such as Technology Development (TD), Process Integration, electrical and physical failure analysis, Product Engineering, Quality Reliability Assurance Team to develop product that meets Quality and Reliability specs and requirements.
Responsibilities include, but not limited to:
- Define & implement Reliability test methodology for new Metal Interconnects and Hybrid Memory process (PWF=Post Wafer Finish/W2W bonding) for the next generation of Micron's memory parts.
- Drive dielectric and W2W Bonding technology roadmaps from Product Quality and Reliability perspective.
- Ensure the device is compliant with Package Level and Wafer Level process Reliability Qualification requirements.
- Collaborate with TD to define the BEOL reliability strategy based on the Process Roadmap.
- Provides periodic updates based on project criticality to stakeholders (including Global Quality (GQ) Leadership and Fab Management) on project status, progress, and roadblocks/opportunities.
- Support technology transfer to production facilities (some international travel may be required).
- Partner with multiple stakeholders in Process Conversion Review Board Meeting (PCRB) to improve coverage from various aspects of product quality and reliability and prevent post qual escapes or excursion triggered by conversion.
- Identify gaps and drive initiatives/programs/business process to build margin around structural, electrical, and reliability performance.
- Partner with TD on latest products and technologies and define quality and reliability fail modes especially NUDD (New, Unique, Different, Difficult) with goal to mitigate risk and achieve high quality materials.
- Build Product Fail Modes Repository based on NUDD (proactive) and previous issues (reactive), and work with key stakeholder to prevent issues or implement effective detections controls and containment.
- Deliver a new Product Fail Modes Repository and their Effective Detection Controls and Containment Document to meet technology development and Transfer timeline.
- Partner with Manufacturing (MFG) or Central Quality teams on current high-volume products to sustain and further develop the Product Fail Modes Repository through regular refresh meeting.
Minimum Qualifications:
- 3+ years’ experience in semiconductor related engineering.
- A Process Engineering or Integration or Assembly & Test background and experience.
- Hands-on experience on Backend of Line Metal Interconnects process (Cu, Al, TSV, Dielectrics) from any Process Module or Process Integration, or Metal Reliability testing (electromigration, High Temperature Storage etc) is strongly desired.
- Knowledge or exposure in Wafer-to-Wafer Bonding technology and failure mode is a strong plus.
- Must possess engineering knowledge of semiconductor processes. Knowledge of NAND Fab processes, flow and fail modes is preferred.
- Highly skilled at problem-solving activity and capability of leading cross functional team.
- Understanding on technical risk assessment, FMEA, and 8D methodology for root cause analysis and problem solving.
- Effective verbal and written communication skills in English.
- Good multitasking skills and ability to set priorities in a fast moving, dynamic environment.
- Ability to work independently, with minimal direction, and a focus on meeting commitments.
- Real passion for improving product quality to increase customer satisfaction.
