THE ROLE:
We are the high-end test engineering team providing test solutions for Data Center Graphics (DCG) New Product Introduction (NPI) under the Product Engineering Organization. We do exciting product development for leading-edge technology that will power the next generation processors used for high performance computing, data centers, enterprise servers, and Artificial Intelligence clusters. If you are looking for a fulfilling and challenging career as an engineer leading NPI ATE Product Development, you are at the right place! As a Senior MTS Product Development Engineer, you will be responsible for developing and driving ATE test solution to meet NPI business milestones and KPI (test time, yield, cost, quality). The expectation is to perform leadership through interaction with design teams, Product & Test Engineering teams, Quality & Reliability teams, software & platform teams to come up with the best solution that balance quality and cost. You will experience working with and learning from AMD’s talented engineering teams around the world.
THE PERSON:
We are looking for someone with strong technical, analytical, leadership and problem-solving skills, as well as demonstrating the characteristic of an independent and resourceful individual.The applicant must have a proficient understanding of DFT(Design-For-Test) architecture for SOC (System-On-Chip) product, a strong test development, Silicon characterization/debug working experience (particularly on Array/Memory BIST) with various industry standard ATE test platforms, as well as data analysis.
KEY RESPONSIBILITIES:
- Accountable to drive test solution/coverage development, optimization to meet business milestone, cost and quality in MBIST area.
- MBIST ATE Test patterns & test flows/method development, debug, test and characterization
- Pre-Silicon engagement with Design, test solution/methodology scoping, planning & validation
- Post Silicon Bring up of test patterns leading to optimization for mass production enablement
- Characterization execution/analysis and debug of MBIST test/fails (including the RMA) in the new silicon designs and process technologies
- Optimization of test coverage and flows for increased quality, yield, cost improvement, and test time reduction
- Conduct engineering evaluations and analysis to drive closure of production issues
- Solves complex, novel, and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation
- Influences technical decisions that have a significant impact on final product
- Involves collaboration on or assuming the consultative or leadership responsibilities for a specific project or for product development initiatives
- May provide technical supervision or mentoring junior engineers.
PREFERRED EXPERIENCE:
- Knowledge or hands-on working experience on Array/Memory Testing (MBIST).
- Good understanding on MBIST DFT architecture and JTAG/TAP, MBIST Repair mechanism and solutions, failure bit-mapping, memory defect models and industry standard MBIST test algorithms.
- Good understanding on SRAM Architecture.
- ATE Test handling/ execution and development experience - Advantest V93K experience preferred. (SMT8 experience is a plus).
- Experience in characterization and data crunching tools - JMP
- Software programming and scripting proficiency (C++, Java, Groovy, Perl, Ruby, Python)
- Proficiency in Windows, and Linux operating systems
- Experience with HVM (High Volume Manufacturing) is a strong plus
- Strong and effective presentation, written and verbal communication skills, and the ability to work with geographically distributed product engineering teams
- Excellent interpersonal, organizational, and analytical skills
- 8 years or more industry experience
- Computer Engineering, or comparable disciplines
ACADEMIC CREDENTIALS:
- BS/MS Electrical Engineering, Computer Engineering, or comparable disciplines
LOCATION:
Singapore
DCG Team
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