Job Description
1st silicon debug, ATE test development, test correlation analysis, product documentation, test limit (guard-band) generation, test time reduction and yield variance control.
• The job scope also requires the engineer to drive for short term and long-term test time reduction and yield improvement to meet set goals without compromising production quality for multiple projects in parallel.
Preferred Qualifications:
• Experience with at least 1 ATE test platform: Teradyne-uFlex, Advantest-93k, NI-STS,
• Experience with development of software such as IGXL, Smart Test, Labview, C# to test Integrated Circuits.
• Knowledge and hands on experience with statistical analysis software package and techniques, quality and reliability testing. Wafer fabrication fundamentals are a plus.
• Solid understanding of electronics engineering fundamentals, digital, analog, mixed-signal, power management and RF circuit analysis techniques.
• Working knowledge of Power Management IC (PMIC) measurement techniques such as line/load regulation, PSRR, transition time, power efficiency, jitter, phase noise, etc.
• Good ASIC device level characterization skills. System level knowledge is a plus.
• Able to work comfortably with lab equipment like Oscilloscopes, Source Meters, Battery Emulators, Spectrum analyzers, etc.
• Able to work independently and with good initiative to overcome technical challenges.
• Strong verbal and written communications skills. Able to organize effectively and document work thoroughly while working with local and remote teams.
• Strong software skills (VB, Python, Perl etc.) for writing and debugging test codes.
• Familiarity with the New Product Introduction process.
• Experience with development of test hardware utilizing team approach, reviewing schematics and layouts.
• Experience troubleshooting hardware and software to develop test solutions.
