Your responsibilities will include, but are not limited to, the following:
- Discover yield issues in NAND development and identify unique metric or combination of metrics, such as wafer/dice/tile shading, ECATS or other custom metric for issues quantification.
- Interact with process area, process integration, yield, failure analysis, product engineering, design, and layout teams to drive clear definition of yield, cell, CMOS, qual, and reliability issues and pareto and derive improvement actions needed across tech-nodes and designs.
- Own and drive non-standard deep dive statistical analysis of inline, probe, cell, and other critical metrics to define issues/problems, enable early inline detection, and improve the product yield and quality. Quantify and track progress on the issue hit hate, line impact, gap to program goal. Quantify yield improvement/downside seen based on process/probe changes.
- Initiate data mining and correlation study on new issue seen. Initiate PFA request to identify root cause of yield issue. Perform inline correlation study to establish inline prediction to yield issue. Make yield projections based on expected improvement/downside. Conduct yield trend analysis, identify root causes in process step, conversion, algorithm change, and design, for yield shift.
- Continuously develop/re-define inline detection in collaboration with metrology and RDA team.
- Identify and define gaps with current test and co-develop (with product, probe, param engineering) unique parametric/probe bins to detect new fail modes as well as validate new program release.
- Collaborate with module owners to identify, quantify key module deficiencies/technology gaps, and drive cross-functional teams to address. Optimize existing layout, conceptualize, and develop innovative solutions to meet product requirements and manufacturability.
- Develop and innovate techniques in extracting data from different databases through various query languages and automate through scripting to improve work efficiency.
- Assist and support the transfer documentation of layout/architecture fundamentals of new technology from R&D to manufacturing fab.
Successful candidates for this position will have:
- Minimum of 3-5 years of experience in the semiconductor industry in the areas of Process Integration, Yield Enhancement, Failure Analysis, Data Science, or Unit Process.
- Ability to develop a strong holistic end to end understanding of PI module on new NAND technologies and related structural & electrical fail mechanisms.
- In-depth knowledge and direct experience with nonvolatile memories along with good understanding of the process flow, interaction of process & device, common yield & reliability issues are desirable.
- Curiosity and natural tendency of learning new things independently.
- Exposure to R&D and transfer/manufacturing is desirable.
- Deep understanding of layout and architecture of NAND product.
- Deep understanding of probe failure mechanism, ability to do electrical bench data collection is desirable.
- Fluency in Python, JavaScript, C or C++ is desirable.
- Ability to be self-motivated and self-governing with proven ability to work in a demanding and dynamic environment.
- Ability to drive and coordinate cross-functional teams to achieve various goals.
- Solid analysis, communication and reporting abilities with demonstrated presentation abilities.
- Ability to travel for extended periods of time to the US or other fabs for collaborative R&D work.
Education:
BS, MS/PhD in Electrical Engineering, Microelectronics, Data Science, Computer Science or related field.
