Job Responsibilities:-
- Utilize in-depth knowledge of Foundation IP to evaluate and qualify IP’s. Able to benchmark and optimize Std cells/IO’s/memory for optimum performance, area or power needs of a project
- Conduct Spice simulations to verify the performance and reliability of designs on RC extracted netlists
- Perform library characterization to ensure accurate timing, power, and area models. Stay up-to-date with industry trends and emerging technologies in library characterization and PPA analysis
- Help to develop and maintain EDA automation scripts to streamline CAD flow and design processes
- Modify and optimize IPQA scripts to improve efficiency and performance
- Analyze and understand both hard and soft IPs within SOC designs. Work with IP vendors to deliver custom specs needed for MXL project needs
- Review silicon reports and provide detailed analysis to identify and resolve issues
- Work closely with vendors and cross-functional teams to ensure successful project outcomes. Collaborate with design teams to ensure seamless integration of libraries and IP blocks
- Maintain comprehensive documentation of IP Vendor engagement. Troubleshoot and resolve issues related to IP, EDA tools and automation flows
Job Requirements:-
- Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, or a related field
- Minimum 10 years of experience in design engineering or a related field. Good understanding of the IC design flow, including front-end and back-end processes
- Proficiency in Foundation IP, Spice Simulation, Library Characterization, EDA automation scripts, and IP script modifications. Familiarity with library characterization tools such as Liberate, Cadence Genus, or Synopsys Library Compiler
- Strong ability to review and analyze silicon reports and provide detailed insights. Excellent analytical and problem-solving skills
- Excellent interpersonal and communication skills for effective collaboration with vendors and team members
- Experience with advanced node technologies (e.g., 8nm, 4nm, and below)
- Experience with SOC IP design and verification
- Knowledge of emerging technologies such as FinFET, FD-SOI, or III-V semiconductors
- Familiarity with industry-standard EDA tools and methodologies
- Experience with tools such as Synopsys PrimeTime, Cadence Genus, or Mentor Graphics Questa
Location: Next to Bendemeer MRT
Interested candidates may submit detailed CV with the following info:-
- Current salary, including AWS or Variable Bonus
- Expected salary
- Availability
