Position Overview:
We are seeking a skilled Physical Design Engineer to join our team. As a Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power checks, power analysis, and signoff for block-level physical implementation. Your expertise in advanced process nodes, low-power design, and automotive chip physical design will contribute to the development of cutting-edge semiconductor products.
Responsibilities:
- Assist in the Physical Design process, supporting RTL to GDS implementation for semiconductor chips.
- Aid in achieving block-level timing closure by assisting with Design constraints optimization and timing analysis.
- Participate in formal checks to ensure designs meet functional and timing requirements.
- Assist with low-power checks and contribute to power consumption analysis for power efficiency optimization.
- Collaborate with the Design team to implement UPF (Unified power Format) for power management and control.
- Support block-level Place and Route (APR), Static timing analysis (STA), and other Physical Design tasks under supervision.
- Contribute to script development in Tcl, Perl, or Python for Design automation and flow enhancement.
Qualification/ Requirements:
- Bachelor’s degree in electrical engineering, Computer Engineering, or a related field.
- Minimum 1 year of experience in physical design for semiconductor chips.
- Basic understanding of RTL-to-GDS flow, timing closure, low-power design, and power analysis concepts.
- Familiarity with scripting languages such as Tcl, Perl, or Python is a plus.
