- RTL-level digital design and problem solving
- Function verification and support
- Digital synthesis, place-and-route, Design for Test and Static timing analysis
- Digital functional verification and FPGA verification
- Fluent in Verilog coding, design, simulation, and verification domains.
- Team player
- Usage of Cadence tools like Incisive Enterprise Simulator, SimVision, Genus, First Encounter, Conformal, Modus, Tempus and Virtuoso will be preferred
x
