We are looking for a Staff Analog Layout Engineer to contribute to the development of High-Speed Connectivity, Broadband Analog and Computing/Storage-Memory Data-Transport products (including functional blocks such as high-speed digital, multi-GHz ADC/DAC, PLL/DLL serial and parallel I/O, and clock generation/distribution for custom ICs). The candidate must have a proven record of laying out high-performance analog circuits in state-of-the-art CMOS process technologies, successfully performed top-level integrations, and placed products into volume production multiple times.
Requirements
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and at least 5+ years of related professional experience.
- Master’s degree in Computer Science, Electrical Engineering or related fields with 3+ professional experience.
- Deep understanding of layout methodology from initial chip planning to tape-out.
- Deep understanding parasitic optimizing in layout
- Experiences in advanced process technology and Fin-FET is preferable.
- Have a high level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
- Have a high-level proficiency/knowledge of Synopsys or CADENCE layout entry tools.
- Programming skills in any of the following are a plus: Skill or Ample or Perl, etc.
- Strong technical and analytical background, problem solving skills, etc.
- Fluent in English
