What you will do
1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek:
- Scan chain insertion & ATPG pattern generation
- Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.)
- Diagnosis to help manufacture process improvement
2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC:
- PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation
- Develop & integrate DFT-related RTL design modules to test chip
What you will bring
- Master's Degree in EEE/ EE/ CE
- Expertise in Synopsys and/or Mentor DFT tools, and HDL simulators like Synopsys VCS
- Fluency in script language including but not limited to TCL/Perl/Python
- Experience about MBIST with state-of-the-art SRAM structure & EDA tools is big plus
- Skill for RTL design & integration, and physical failure analysis(PFA) will also be plus
- Ability to think and work independently with different teams
- Interest in understanding more details in entire design flow
- Ability to use English for discussing technical details
- With a minimum of 7 years relevant industrial work experience
About the company
MediaTek Incorporated (TWSE: 2454) is the world’s 5th largest global fabless semiconductor company. Joining MediaTek means becoming part of a team that powers over 2 billion ICs worldwide, enriching and enhancing everyday life. Our chipsets are integral to a wide range of products, from smartphones, mobile devices to home and IoT devices, in entertainment and multimedia products, and provide connectivity and communication solutions that keep people connected with friends and their families with access to online resources. Working at MediaTek offers you the opportunity to contribute to the world through the devices we use in our daily lives – it’s more than just a job, it’s a chance to make a meaningful impact.
