Job responsibilities
1. Responsible for Physical Design for Full chip/Blocks covering Floor planning, Placement, Area Optimization, Clock tree synthesis, Placement optimizations, Routing, Timing Closure, power network design, Voltage drop analysis, RC extraction, etc.
2. Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other R&D Engineers.
3. Work with Frontend team to understand the RTL design and drive physical aspects early in design cycle for physical design closure.
Job requirements
1. Bachelor's degree or above, major in Microelectronics / Electronic engineering / Communication engineering and other related fields.
2. More than 3 years working experience in layout and wiring of 40 nm and below technology.
3. Able to independently complete the whole chip P&R process and IR_ Drop, STA, low power inspection.
4. Familiar with TCL or Perl and other scripting languages.
5. Familiar with design flows and EDA tool software.
6. Familiar with Sign-off methodology and the use of EDA tool software in STA / power.
