Total 3 staff nurse job vacancies in Art / Design / Entertainment category in Singapore

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.

Available Job Responsibilities

• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and layout integration of design components
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Help specify silicon test plan and correlate silicon to simulation data

Preferred Skills

• Good understanding of transistor level circuit behavior and device physics
• Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Proficiency in running simulators, writing automation scripts, and are tools savvy
• Understanding of memory behavioral and physical models is a plus
• Expertise in memory circuit design is a plus
• Understanding of DFT schemes and chip level integration is a plus
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking
• Passion for solving complex problems and willingness to learn

Qualifications

Requires a BS in Electrical or Computer Engineering and > 5 years of related experience

Skills and responsibilities:

• Utilize commercial and in-house EDA tools (e.g. Synopsys, Cadence, Siemens) for the design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies.
• Proficient with a full Netlist/Gates to GDS flow, inclusive of all construction stages (e.g. RTL synthesis, placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis) for complex digital blocks of up to 12Mgates/3M instances with embedded macros. Ability to handle multiple block assignments in parallel is required.
• Proficiency in UNIX/Linux and scripting languages is advantageous.

Required Qualifications:

• Degree, Masters or PhD in Electrical/Electronics/Computer engineering.
• Minimum of 5 years or more experience in a relevant field.

We have an exciting position in the explosive growth area of Data Center Enterprise Storage. In this role you will be responsible for developing the most advanced semiconductor devices to support stringent high capacity storage needs across all the top tier service providers. Our IC R&D team is looking for an experienced physical design engineer to develop high speed custom analog/mixed signal products for the storage industry. A qualified applicant would work closely with circuit design engineers to lay out high-speed custom analog designs and develop mask layouts for customer products, as well as printed circuit board designs. You will join a cross-functional team responsible for developing leading edge high-speed custom IC products that ultimately achieve high volume production.

Job Responsibilities

• Lay out high speed, high performance analog/mixed-signal custom integrated circuits
• Work directly with a team of engineers to determine floor plan, routing and I/O requirements
• Perform IC design rule and connectivity verification and drive products through mask release flows.
• Contribute to methodology improvements to increase layout and verification efficiency.
• Create reticle layouts, documentation, and PO’s to release products for mask build.
• Complete PCB layouts for test hardware.

Requirements/Qualifications:

• Bachelor's degree in Electrical Engineering (or related field)
• Minimum 8 years experience in custom analog IC physical design
• Experience with schematic-driven layout, floor planning, chip level routing, design for manufacturing and design rule and connectivity verification is preferred
• Experience using Cadence Virtuoso XL preferred
• Experience with Cadence Allegro for PCB layout preferred
• Familiarity with both analog and digital layout tools and flows, circuit design concepts and IC manufacturing processes desired
• Strong communication skills, proficiency in both oral and written English
• Understanding of silicon process technologies (CMOS and Bipolar) and device physics would be a plus
• Proven analytical skills (application of math and physics to solve problems)
• Must be meticulous and demonstrate attention to detail.